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Through Wafer Interconnects for 3-D Packaging

Published online by Cambridge University Press:  26 February 2011

Amy J. Moll ,
William B. Knowlton  and
Rex Oxford
Amy J. Moll
Affiliation:
amoll@boisestate.edu, Boise State University, Materials Science & Engineering, 1910 Univ Dr, Boise, ID, 83725-2075, United States, 208-426-5719
William B. Knowlton
Affiliation:
bknowlton@boisestate.edu, Boise State University, Materials Science & Engineering, Boise, ID, 83725-2075, United States
Rex Oxford
Affiliation:
roxford@boisestate.edu, Boise State University, Materials Science & Engineering, Boise, ID, 83725-2075, United States
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Abstract

Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.

Keywords

packagingSielectronic material
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y01-06
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

1. Karnezos, M., “3D packaging: where all technologies come together,” IEEE/CPMT/Semi 29th International Electronics Manufacturing Symposium. 2004.Google Scholar
2. Kada, M. and Smith, L., “Advancements in Stacked Chip Scale Packaging Provides System in a Package Functionality for Wireless and Handheld Applications,” Proceedings of the Pan Pacific Microelectronics Symposium Conference. 2000.Google Scholar
3. Karnezos, M., “Stacked-die packaging: technology toolbox,” Advanced Packaging, Vol.13, No.8 (2004), pp. 41–4.Google Scholar
4. Liu, C., “Through-Wafer Electrical Interconnects by Sidewall Photolighographic Patterning,” IEEE Instrumentation and Measurement Technology Conference, St. Paul, Minnesota. 1998.Google Scholar
5. Hoshino, M. et al., “Wafer Process and Issue of Through Electrode in Si wafer Using Cu Damascene for Three Dimensional Chip Stacking,” Proceedings of IEEE Interconnect Technology Conference, 2002.Google Scholar
6. Burkett, S.L., et al., Advance processing techniques for through-wafer interconnects. Journal of Vacuum Science and Technology B, 2004. 22(1): p. 248–256.Google Scholar
7. Kenoyer, L., Oxford, R., and A.J. Moll., “Optimization of Bosch etch process for through wafer interconnects,” Biennial/University/Government/Industry Microelectronics Symposium, Boise, ID, April. 2003.Google Scholar
8. Craigie, C.J.D., Burkett, S., Sheehan, T., Johnson, V.N., Moll, A.J., Knowlton, W.B., “Polymer thickness effects on Bosch etch profiles”, Journal of Vacuum Science and Technology B 20, 2229 (2002).Google Scholar
9. Miranda, P.A., Imonigie, J., and Moll, A.J., “Through-Wafer Interconnect CMP: An Investigationn of Slurry Interaction Effects using a Design of Experiments Approach,” Journal of the Electrochemical Society, 153 (3) G211–G217 (2006)Google Scholar
10. Lawrence, T.E., et al., “Electrical characterization of through-wafer interconnects,” IEEE Workshop on Microelectronics and Electron Devices, Boise, ID, April. 2004.Google Scholar
11. Jozwiak, J., IIISouthwick, R.G., Johnson, V.N., Knowlton, W.B., and Moll, A.J., “Integrating Through-Wafer Interconnects with Active Device and Circuits,” IEEE Transactions on Advanced Packaging, Submitted (4/10/06)Google Scholar