Symposium B – Advanced Metallization for Devices and Circuits—Science, Technology and Manufacturing III
Research Article
Interconnection Technology for Modern Logic Devices; an Exercise in System Engineering to Assure Manufacturability
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- 25 February 2011, 3
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Manufacturing Considerations for VLSI Interconnect Systems
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- 25 February 2011, 13
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Process Integration and Manufacturasility Issues for High Performance Multilevel Interconnect
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- 25 February 2011, 25
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High Performance Metallization Issues for Ulsi
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- 25 February 2011, 33
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Copper Metallization Manufacturing Issues for Future ICs
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- 25 February 2011, 41
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Manufacturability Versus Reliability Issues Relevant to Interconnect Metallizations.
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- 25 February 2011, 59
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Designing and Building Reliability Into VLSI Interconnect Systems
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- 25 February 2011, 71
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A Multilayer Interconnect Process for 0.5um Logic Technology
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- 25 February 2011, 81
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Basic Science in Silica Glass Polishing
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- 25 February 2011, 89
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Chemical Mechanical Polishing for Planarization in Manufacturing Environment
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- 25 February 2011, 99
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The Evolution of Chem-Mechanical Planarization: From Aberrant to Prosaic
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- 25 February 2011, 105
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Consumables for the Chemical Mechanical Polishing (Cmp) of Dielectrics and Conductors
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- 25 February 2011, 121
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Surface Layer Formation During the Chemical Mechanical Polishing of Copper Thin Films
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- 25 February 2011, 133
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Characterization of Chemical-Mechanical Polishing Dielectrics for Multilevel Metallization
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- 25 February 2011, 139
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Chemical-Mechanical Polishing of Tungsten with Hologen-Based Slurries
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- 25 February 2011, 145
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Planarization Ability of Chemical Mechanical Planarization (Cmp) Processes
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- 25 February 2011, 151
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The Surface Damage in SiO2 Caused by Chemical Mechanical Polishing on Ic-60 Pads
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- 25 February 2011, 157
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Surface and Interface Modification of Copper for Electronic Application
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- 25 February 2011, 169
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Surface Effects in the Mocvd of Copper
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- 25 February 2011, 177
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Growth Kinetics and Materials Properties of Cu5Si
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- 25 February 2011, 189
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