Introduction

The gate resistance Rg (Figure 15.16) has long been recognized as a very important parasitic parameter that can be difficult to reduce to an acceptable value. Rg degrades the noise figure and power gain. For the field-effect transistor (FET) depicted in Figure 14.1, the gate and drain voltages (and source ground) are applied to metal pads outside the active FET area. The gate, drain and source metallizations carry the currents laterally in the yz-plane onto the active FET area, and deliver the currents in an essentially uniform fashion in the x direction to the semiconductor. For the source and drain this is typically not a problem because of their larger extension in the y direction, and the thick interconnect metallizations available (neither is shown in Figure 14.1, which only depicts the central core of the device). The source and drain resistances (Rs and Rd) are thus not limited by the metallization resistance, but by the contact and semiconductor components discussed in Section 14.6.2. The situation is different for the gate because of its much smaller extension in the y direction. Consequently, in order to reduce the gate resistance for submicron gates, much effort has gone into developing T-gate processes (Figure 14.1; Section 17.7). This chapter will show that there is much more to the gate resistance, and therefore that there are additional ways to reduce it. In particular, we will discuss an interfacial component which, in its purest form, is intimately tied to the mechanism responsible for Schottky-barrier formation.