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3 - Characteristics, performance, modeling, and reliability of CMOS technologies for mm-wave power amplifiers

Published online by Cambridge University Press:  05 April 2016

By
Antonino Scuderi  and
Egidio Ragonese
Edited by
Hossein Hashemi  and
Sanjay Raman
Antonino Scuderi
Affiliation:
Qualcomm
Egidio Ragonese
Affiliation:
ST-Microelectronics
Hossein Hashemi
Affiliation:
University of Southern California
Sanjay Raman
Affiliation:
Virginia Polytechnic Institute and State University
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Summary

Introduction

CMOS technology is a new player in the scenario of mm-wave technologies. Only at the beginning of the 1990s did the scientific community start to consider CMOS for RF applications and it was only at the beginning of the new millennium that aggressive dimensional scaling allowed us to figure out its exploitation at mm-waves. The dimensional scaling produced higher unity current-gain cut-off frequency (fT) and maximum oscillation frequency (fmax), at the expense of a lower breakdown voltage. Classical small-signal high-frequency building blocks (i.e. low-noise amplifiers) can manage the reduced supply voltage as the main impact is related to the available voltage dynamic. Different considerations have to be made for power amplifiers (PAs) as the inherent power performance is directly connected with the allowed voltage swing. Indeed, the generation of a 1-W power level on a 50-ohm load would require a sinusoidal voltage of 10 V (i.e. 20-vpp swing) that is not compliant with the typical breakdown voltage of submicron CMOS technologies. In order to reduce the swing on active devices, impedance transformation is needed. The problem with classical matching networks is that, when increasing the transformation ratio, very low impedance at the transistor level has to be managed. This would require a very-high-quality matching network to avoid losses [1, 2]. Passive components, mainly spiral inductors and transformers, cannot achieve very high quality factors (Q-factor), especially on CMOS conductive bulk. Silicon-on-insulator (SOI) processes can help in giving a solution for compact and high-performance integration of matching networks at the expense of higher costs.

A second basic constraint for the design of a CMOS amplifier is the gain limitation due to high input/output capacitances (i.e. intrinsic fmax limitation) and source inductive parasitics. Finally, the dimensional scaling also causes a relative increase of resistive parasitics with a direct impact on the amplifier efficiency. Indeed, since impedance transformation is related to the conversion of voltage swing into current swing, any resistive contribution would generate higher losses on high-current paths.

The nonlinear parasitics as well as the knee voltage (i.e. the voltage at which there occurs the transition from “linear” to “saturation” in the IDS-VDS characteristic) and oxide traps also impact the overall device linearity performance that is of utmost importance in modern communication systems.

Type
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Information
mm-Wave Silicon Power Amplifiers and Transmitters , pp. 77 - 138
Publisher: Cambridge University Press
Print publication year: 2016

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