Background

Minimizing the gate oxide charge is a frequent challenge in the development of metal–oxide–semiconductor (MOS) technology. The original procedures were developed at the time when SiO2 was the dominating gate insulator in MOS technology and detailed descriptions of the capture processes involved in these different experimental situations are seldom treated in the literature. Due to the need for device characterization, electrical methods dominate. Few luminescence results have been published, whereas the detailed character of oxide traps has been learnt mainly from electron spin resonance (ESR) data (see Chapters 9–11).

In recent years, especially when electrical methods have been practiced on high-k oxides with interlayers close to the silicon face, the electric field distribution in this environment is more complicated, which increases the complexity of interpreting measured data. In the present chapter, we will expound the charge carrier statistics for oxide traps, the variations in capture mechanisms and the processes between different capture conditions, and analyze their influence on experiments for quantifying capture cross sections of high-k oxide traps. We will mainly study the common techniques for injecting charge into oxide traps by electric fields, using MOS capacitors and transistors. Also, we will peel off a couple of sample dependent properties at some expense of quantitative precision by using two important approximations by (i) assuming that the concentration of electrons available for injection from the semiconductor into the oxide has a constant relation to the effective density of states in the semiconductor conduction band and (ii) neglecting the influence of captured charge on the potential distribution inside the oxide. Furthermore, all reasoning will be limited to electron injection and capture but can readily be turned into corresponding arguments for hole processes.