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  • Cited by 23
Publisher:
Cambridge University Press
Online publication date:
January 2012
Print publication year:
2011
Online ISBN:
9780511794292

Book description

Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.

Reviews

‘Advanced Data Converters provides a comprehensive overview and comparison of numerous architectures and techniques that are central to understanding modern data converter design, selection, and application. The book explores not only the 'what?' and the 'how?', but also the 'why?', providing the reader with insights into the factors that drive the trade-offs in modern converter designs. The material is presented in an approachable manner, it reads like a tutorial by a friend who is an expert in the field.’

David Robertson - Analog Devices

‘The field of data conversion has been following a steep trajectory that is hard to track even for experienced designers. Manganaro’s book fulfils a critical role in capturing the most significant advancements of the past decade in a refreshingly intuitive format; I look forward to having this monograph in my library.’

Boris Murmann - Stanford University

‘Data converters are used more and more by electronic systems. The requests of designers and users to better [understand] architectures and to know practical aspects is appropriately satisfied by [this book]. It is surely a precious working aid for professionals but also is a valid help for graduate students [who] can find in the book the necessary background notions and valuable information on architectures, practical limits and design tricks. The comprehensive list of references is a unique source of additional information. It complements and makes … the book [more valuable].’

Franco Maloberti - University of Pavia, Italy

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Contents

References
[1] Inouye, S., Robles-Bruce, M., and Scherer, M., “2009 data converters,” Databeans Inc., Reno, NV, technical report, June 2009.
[2] Inouye, S., Robles-Bruce, M., and Scherer, M., “2010 data converters,” Databeans Inc., Reno, NV, technical report, June 2010.
[3] Bult, K., “Embedded analog-to-digital converters,” in European Solid-State Circuits Conference, 2009, pp. 52–64.
[4] Kester, W., “Precision measurement and sensor conditioning,” in The Data Conversion Handbook, Kester, W., Ed. Elsevier, Burlington, MA, 2005, pp. 539–561.
[5] Geiger, R. L., Allen, P. E., and Strader, N. R., VLSI: Design Techniques for Analog and Digital Circuits, Electronic Engineering Series. McGraw-Hill, New York, NY, 1990.
[6] Márkus, J., Silva, J., and Temes, G. C., “Theory and applications of incremental Δ–Σ converters,” IEEE Transactions on Circuits and Systems – Part I, vol. 51, no. 4, pp. 678–690, 2004.
[7] Kester, W., “Digital audio,” in The Data Conversion Handbook, Kester, W., Ed. Elsevier, Burlington, MA, 2005, pp. 591–605.
[8] Conti, J. P., “Wake up to wireless,” IET Engineering & Technology, vol. 5, no. 13, pp. 14–15, 2010.
[9] Sheikholeslami, A., “ISSCC 2011 forum on high-speed transceivers: Standards, challenges, and future,” in International Solid-State Circuits Conference, IEEE, 2011.
[10] Kester, W., “Software radio and IF sampling,” in The Data Conversion Handbook, Kester, W., Ed. Elsevier, Burlington, MA, 2005, pp. 633–666.
[11] Garg, V. K. and Wilkes, J. E., Wireless and Personal Communication Systems. Prentice Hall, New York, NY, 1996.
[12] Hendriks, P., “Specifying communications DAC's,” IEEE Spectrum, vol. 34, no. 7, pp. 58–69, 1997.
[13] Edwards, C., “In the balance,” IET Engineering & Technology, vol. 5, no. 14, pp. 60–62, 2010.
[14] Manganaro, G. and Leenaerts, D., “ISSCC 2011 forum on advanced transmitters for wireless infrastructure,” in International Solid-State Circuits Conference, IEEE, 2011.
[15] Abidi, A. A., “The path to the software-defined radio receiver,” IEEE International Journal of Solid State Circuits, vol. 42, no. 5, pp. 954–966, 2007.
[16] Kenington, P. B. and Astier, L., “Power consumption of A/D converters for software radio applications,” IEEE Transactions on Vehicular Technology, vol. 49, no. 2, pp. 643–650, 2000.
[17] Sevenhans, J. and Chang, Z.-Y., “A/D and D/A conversion for telecommunication,” IEEE Circuits & Devices Magazine, vol. 14, no. 1, pp. 32–42, 1998.
[18] Breems, L. and Huijsing, J. H., Continuous-Time Sigma–Delta Modulation for A/D Conversion in Radio Receivers. Kluwer, Dordrecht, the Netherlands, 2001.
[19] EE Times editors, “Medical electronics gets personal,” http://www.nxtbook.com/nxtbooks/cmp/eetimes\_medelec\_20101108/\#/3/OnePage, 2010.
[20] Hammerschmidt, C., “National Semi to commercialize sigma delta ADC,” http://www.eetimes.com/electronics-news/4190836/National-Semi-to-commercialize-Sigma-Delta-ADC, 2008.
[21] Stagni, C., Guiducci, C., Benini, L.et al., “CMOS DNA sensor array with integrated A/D conversion based on label-free capacitance measurement,” IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 2956–2964, 2006.
[22] Wong, A. C.-W., McDonagh, D., Kathiresan, G.et al., “A 1 V, micropower system-on-chip for vital-sign monitoring in wireless body sensor networks,” in International Solid-State Circuits Conference, 2008, pp. 138–139.
[23] Chou, S., “Integration and innovation in the nanoelectronics era,” in International Solid-State Circuits Conference, 2005, pp. 36–41.
[24] Chen, T.-C., “Where CMOS is going: Trendy hype vs. real technology,” in International Solid-State Circuits Conference, 2006, pp. 22–28.
[25] Moore, G., “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 114–117, 1965.
[26] Moore, G., “No exponential is forever: But ‘forever’ can be delayed!,” in International Solid-State Circuits Conference, 2003, pp. 20–23.
[27] Edwards, C., “Analogue circuits squeeze chip design,” IET Engineering & Technology, vol. 5, no. 8, pp. 14–15, 2010.
[28] Chiu, Y., Nikolić, B., and Gray, P. R., “Scaling of analog-to-digital converters into ultra-deepsubmicron CMOS,” in Custom Integrated Circuits Conference, 2005, pp. 375–382.
[29] Bult, K., “The effect of technology scaling on power dissipation in analog circuits,” in Analog Circuit Design, Steyaert, M., Roermund, A. H., and Huijsing, J. H., Eds. Springer-Verlag, Berlin, Germany, 2006, pp. 251–290.
[30] Bult, K., “Analog design in deep sub-micron CMOS,” in European Solid-State Circuits Conference, 2000, pp. 126–132.
[31] Murmann, B., Nikaeen, P., Connelly, D. J., and Dutton, R. W., “Impact of scaling on analog performance and associated modeling needs,” IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2160–2167, 2006.
[32] Boulemnakher, M., Andre, E., Roux, J., and Paillardet, F., “A 1.2V 4.5mW 10 b 100 MS/s pipeline ADC in a 65 nm CMOS,” in International Solid-State Circuits Conference, 2008, pp. 250–251.
[33] Johns, D. and Martin, K., Analog Integrated Circuit Design. John Wiley & Sons, NewYork, NY, 1997.
[34] Maloberti, F., Data Converters. Springer-Verlag, Berlin, Germany, 2009.
[35] Thomsen, A., Kasha, D., and Lee, W., “A five stage chopper stabilized instrumentation amplifier using feedforward compensation,” in VLSI Circuits Conference, 1998, pp. 220–223.
[36] Yan, J. and Geiger, R. L., “Fast-settling amplifier design using feedforward compensation technique,” in IEEE Midwest Symposium on Circuits and Systems, 2000, pp. 494–498.
[37] Moyal, M., Groepl, M., Werker, H., Mitteregger, G., and Schambacher, J., “A 700/900 mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5 dBm line drivers,” in International Solid-State Circuits Conference, 2003, pp. 416–417.
[38] Harrison, J. and Weste, N., “A 500MHz CMOS anti-aliasing filter using feed-forward opamps with local common-mode feedback,” in International Solid-State Circuits Conference, 2003, pp. 132–133.
[39] Thandri, B. K. and Silva-Martínez, J., “A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors,” IEEE International Journal of Solid State Circuits, vol. 38, no. 2, pp. 237–243, 2003.
[40] Ito, R. and Itakura, T., “Phase compensation techniques for low-power operational amplifiers,” IEICE Transactions on Electronics, vol. 93-C, no. 6, pp. 730–740, 2010.
[41] Abo, A. M. and Gray, P. R., “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE International Journal of Solid State Circuits, vol. 34, no. 5, pp. 599–606, 1999.
[42] Pelgrom, M. J., Duinmaijer, A. C. J., and Welbers, A. P. G., “Matching properties of MOS transistors,” IEEE International Journal of Solid State Circuits, vol. 24, no. 5, pp. 1433– 1440, 1989.
[43] Kinget, P. R., “Device mismatch and tradeoffs in the design of analog circuits,” IEEE International Journal of Solid State Circuits, vol. 40, no. 6, pp. 1212–1224, 2005.
[44] Drennan, P. G. and McAndrew, C. C., “Understanding MOSFET mismatch for analog design,” IEEE International Journal of Solid State Circuits, vol. 38, no. 3, pp. 450–456, 2003.
[45] Wong, B. P., Zach, F., Moroz, V.et al., Eds., Nano-CMOS Design for Manufacturability. John Wiley & Sons, New York, NJ, 2009.
[46] Pang, L.-T. and Nikolíc, B., “Measurements and analysis of process variability in 90 nm CMOS,” IEEE International Journal of Solid State Circuits, vol. 44, no. 5, pp. 1655–1663, 2009.
[47] Hurwitz, J., “ISSCC 2011 tutorial on layout: The other half of nanometer analog design,” in International Solid-State Circuits Conference, IEEE, 2011.
[48] Ali, A. M. A., Morgan, A., Dillon, C. et al., “A 16 b 250 MS/s IF-sampling pipelined A/D converter with background calibration,” IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2602–2612, 2010.
[49] Payne, R., Corsi, M., Smith, D., Kaylor, S., and Hsieh, D., “A 16 b 100-to-160 MS/s SiGe BiCMOS pipelined ADC with 100 dBFS SFDR,” in International Solid-State Circuits Conference, 2010, pp. 294–295.
[50] Robertson, D. and Montalvo, T., “Issues and trends in RF and mixed signal integration and partitioning,” IEEE Communications Magazine, vol. 46, no. 9, pp. 52–56, 2008.
[51] Robertson, D. and Kessler, M., “Smart partitioning,” in The Data Conversion Handbook, Kester, W., Ed. Elsevier, Burlington, MA, 2005, pp. 273–280.
[52] Razavi, B., Principles of Data Conversion System Design. IEEE Press, Piscataway, NJ, 1995.
[53] Plassche, R. J., CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edn. Kluwer, Dordrecht, the Netherlands, 2003.
[54] Murmann, B., EE315: VLSI Data Conversion Circuits – Class Notes. Stanford University, Stanford, CA, 2008.
[55] Kester, W., “The importance of data converter static specifications – don't lose sight of the basics!,” Analog Devices, Tutorial MT-010, 2009.
[56] ,Maxim Staff, “INL/DNL measurements for high-speed analog-to-digital converters (ADCs),” Maxim Integrated Products, Application Note 283, 2001.
[57] Figueiredo, P. M. and Vital, J. C., Offset reduction techniques in high-speed analog-to-digital converters. Springer-Verlag, Berlin, Germany, 2009.
[58] Brannon, B., “Overcoming converter nonlinearities with dither,” Analog Devices, Application Note AN-410, 1995.
[59] Kester, W. and Bryant, J., “Data converter AC errors,” in The Data Conversion Handbook, Kester, W., Ed. Elsevier, Burlington, MA, 2005, pp. 83–122.
[60] Kester, W., Ed., The Data Conversion Handbook. Elsevier, Burlington, MA, 2005.
[61] Singer, L. A. and Brooks, T. L., “A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter,” in VLSI Circuits Conference, 1996, pp. 94–95.
[62] Li, J., LeBoeuf, R., Courcy, M., and Manganaro, G., “A 1.8V 10b 210MS/s CMOS pipelined ADC featuring 86dB SFDRwithout calibration,” in Custom Integrated Circuits Conference, 2007, pp. 317–320.
[63] Mercer, D. A., “Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-μm CMOS,” IEEE International Journal of Solid State Circuits, vol. 42, no. 8, pp. 1688–1698, 2007.
[64] Hastings, A., The Art of Analog Layout, 2nd edn. Prentice Hall, New York, NY, 2005.
[65] Enz, C. C. and Temes, G. C., “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proceedings of the IEEE, vol. 84, no. 11, pp. 1584–1614, 1996.
[66] Yang, J. and Lee, H.-S., “A CMOS 12-bit 4 MHz pipelined A/D converter with commutative feedback capacitor,” in Custom Integrated Circuits Conference, 1996, pp. 427–430.
[67] Galton, I. and Carbone, P., “A rigorous error analysis of D/A conversion with dynamic element matching,” IEEE Transactions on Circuits and Systems – Part II, vol. 42, no. 12, pp. 763–772, 1995.
[68] Galton, I., “Why dynamic-element-matching DACs work,” IEEE Transactions on Circuits and Systems – Part II, vol. 57, no. 2, pp. 69–74, 2010.
[69] Devarajan, S., Singer, L., Kelly, D.et al., “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC,” IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3305–3313, 2009.
[70] Grob, B. and Herndon, C., Basic Television and Video Systems, 6th edn. McGraw-Hill, New York, NY, 1998.
[71] Chaudhry, I. A., Kwak, S.-U., Manganaro, G., Sarraj, M., and Viswanathan, T. L., “A triple 8 b, 80MSPS, 3.3V graphics digitizer,” in IEEE International Symposium on Circuits and Systems, vol. 5, 2000, pp. 557–560.
[72] Li, J., Manganaro, G., Courcy, M., Min, B.-M., Tomasi, L., Alam, A., and Taylor, R., “A 10b 170 MS/s CMOS pipelined ADC featuring 84dB SFDR without calibration,” in VLSI Circuits Conference, 2006, pp. 226–227.
[73] Taft, R. C., Menkus, C. A., Tursi, M. R., Hidri, O., and Pons, V., “A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency,” IEEE International Journal of Solid State Circuits, vol. 39, no. 12, pp. 2107–2115, 2004.
[74] Gustavsson, M., Wikner, J. J., and Tan, N. N., CMOS Data Converters for Communications. Kluwer, Dordrecht, the Netherlands, 2000.
[75] Metzler, B., Audio Measurement Handbook, 1st edn. Audio Precision, Inc., Beaverton, OR, 1993.
[76] Motschenbacher, C. and Connelly, J., Low Noise Electronic System Design. John Wiley & Sons, New York, NY, 1993.
[77] Munson, J., “Understanding high-speed DAC testing and evaluation,” Analog Devices, Application Note AN-928, 2008.
[78] Wambacq, P. and Sansen, W., Distortion Analysis of Analog Integrated Circuits. Kluwer, Dordrecht, the Netherlands, 1998.
[79] Brannon, B., “Sampled systems and the effects of clock phase noise and jitter,” Analog Devices, Application Note AN-756, 2004.
[80] Walden, R. H., “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539–550, 1999.
[81] Schreier, R. and Temes, G. C., Understanding Delta–Sigma Data Converters. John Wiley & Sons, New York, NY, 2005.
[82] Murmann, B., “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Custom Integrated Circuits Conference, 2008, pp. 105–112.
[83] Lee, H.-S. and Sodini, C. G., “Analog-to-digital converters digitizing the analog world,” Proceedings of the IEEE, vol. 96, no. 2, pp. 323–334, 2008.
[84] Jonsson, B. E., “A survey of A/D-converter performance evolution,” in IEEE International Conference on Electronics, Circuits, and Systems, 2010, pp. 768–771.
[85] Murmann, B., “ADC performance survey 1997–2011,” http://www.stanford.edu/∼murmann/adcsurvey.html, 2011.
[86] Palmers, P. and Steyaert, M. S. J., “A 10-bit, 1.6 GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS,” IEEE Transactions on Circuits and Systems – Part I, no. 11, pp. 2870–2879, 2010.
[87] Bosch, A., Steyaert, M. S. J., and Sansen, W., “Solving static and dynamic performance limitations for high-speed D/A converters,” in Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers, Huijsing, J. H., Steyaert, M., and Roermund, A., Eds. Kluwer, Dordrecht, the Netherlands, 2002, pp. 189–210.
[88] Giotta, D., Pessl, P., Clara, M., Klatzer, W., and Gaggl, R., “Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13 μm CMOS,” in European Solid-State Circuits Conference, 2004, pp. 163–166.
[89] Clara, M., Klatzer, W., Seger, B., Giandomenico, A. Di, and Gori, L., “A 1.5V 200 MS/s 13 b 25mW DAC with randomized nested background calibration in 0.13 μm CMOS,” in International Solid-State Circuits Conference, 2007, pp. 250–251.
[90] Lin, C.-H., Goes, F. M. L., Westra, J.R.et al., “A12 bit 2.9 GS/sDAC with IM3 < -60 dBc beyond 1 GHz in 65 nm CMOS,” IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3285–3293, 2009.
[91] Reeder, R., Green, W., and Shillito, R., “Analog-to-digital converter clock optimization: A test engineering perspective,” Analog Dialogue, vol. 42, no. 2, pp. 1–7, 2008.
[92] Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, 4th edn. John Wiley & Sons, New York, NY, 2001.
[93] Brokaw, A. P., “A temperature sensor with single resistor set-point programming,” IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 1908–1915, 1996.
[94] Holloway, P. R. and Wan, J., “Emitter area trim scheme for a PTAT current source,” US Patent 7 443 226, 2007.
[95] Holloway, P. R. and Wan, J., “Self-regulating process-error trimmable PTAT current source,” US Patent 7 236 048, 2007.
[96] Ge, G., Zhang, C., Hoogzaad, G., and Makinwa, K., “A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from -40°C to 125°C,” in International Solid-State Circuits Conference, 2010, pp. 78–79.
[97] Baginski, P., Brokaw, P., and Wurcer, S., “A complete 18-bit audio D/A converter,” in International Solid-State Circuits Conference, 1990, pp. 202–203.
[98] Moon, U.-K. and Song, B.-S., “Background digital calibration techniques for pipelined ADC's,” IEEE Transactions on Circuits and Systems – Part II, vol. 44, no. 2, pp. 102–109, 1997.
[99] Kwak, S.-U., Song, B.-S., and Bacrania, K. L., “A 15-b, 5-Msample/s low-spurious CMOS ADC,” IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1866–1875, 1997.
[100] Lee, H.-S., Hodges, D. A., and Gray, P. R., “A self-calibrating 15 bit CMOS A/D converter,” IEEE International Journal of Solid State Circuits, vol. 19, no. 6, pp. 813–819, 1984.
[101] Karanicolas, A., Lee, H.-S., and Bacrania, K. L., “A 15-b 1-Msample/s digitally selfcalibrated pipeline ADC,” IEEE International Journal of Solid State Circuits, vol. 28, no. 12, pp. 1207–1215, 1993.
[102] Raol, J. R., Girjia, G., and Singh, J., Modelling and Parameter Estimation of Dynamic Systems. IEE Control Engineering. Institution of Engineering and Technology (IET) London, 2004.
[103] Levy, B. C., Principles of Signal Detection and Parameter Estimation. Springer-Verlag, Berlin, Germany, 2009.
[104] Bos, A., Parameter Estimation for Scientists and Engineers. John Wiley & Sons, New York, NY, 2007.
[105] Gregorian, R. and Temes, G. C., Analog MOS Integrated Circuits for Signal Processing. John Wiley & Sons, New York, NY, 1986.
[106] Murmann, B. and Gopinathan, V., “ISSCC 2011 evening session on data converter breakthrough in retrospect,” in International Solid-State Circuits Conference, IEEE, 2011.
[107] Plassche, R. J. and Grift, R. E. J., “A high-speed 7 bit A/D converter,” IEEE International Journal of Solid State Circuits, vol. 14, no. 6, pp. 938–943, 1979.
[108] Bult, K. and Buchwald, A., “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1887–1895, 1997.
[109] Kattmann, K. and Barrow, J., “A technique for reducing differential non-linearity errors in flash A/D converters,” in International Solid-State Circuits Conference, 1991, pp. 170–171.
[110] Pan, H. and Abidi, A. A., “Spatial filtering in flash A/D converters,” IEEE Transactions on Circuits and Systems – Part II, vol. 50, no. 8, pp. 424–436, 2003.
[111] Nagaraj, K., Martin, D. A., Wolfe, M.et al., “A dual-mode 700-Msamples/s 6-bit 200- Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process,” IEEE International Journal of Solid State Circuits, vol. 35, no. 12, pp. 1760–1768, 2000.
[112] Choi, M. and Abidi, A. A., “A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS,” IEEE International Journal of Solid State Circuits, vol. 36, no. 12, pp. 1847–1858, 2001.
[113] Scholtens, P. C. S. and Vertregt, M., “A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination,” IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1599–1609, 2002.
[114] Park, Y.-I., Karthikeyan, S., Tsay, F., and Bartolome, E., “A 10 b 100 MSample/s CMOS pipelined ADC with 1.8V power supply,” in International Solid-State Circuits Conference, 2001, pp. 580–583.
[115] Poulton, K., Neff, R., Muto, A.et al., “A 4 GSample/s 8 b ADC in 0.35 μm CMOS,” in International Solid-State Circuits Conference, 2002, pp. 166–167.
[116] Poulton, K., Neff, R., Setterberg, B.et al., “A 20GS/s 8 b ADC with a 1MB memory in 0.18 μm CMOS,” in International Solid-State Circuits Conference, 2003, pp. 318–319.
[117] Manganaro, G., “Feed-forward approach for timing skew in interleaved and double-sampled circuits,” IEE Electronics Letters, vol. 37, no. 9, pp. 552–553, 2001.
[118] Li, Y. and Sánchez-Sinencio, E., “A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC,” IEEE International Journal of Solid State Circuits, vol. 38, no. 8, pp. 1405–1410, 2003.
[119] Geelen, G. and Paulus, E., “An 8 b 600 MS/s 200mW CMOS folding A/D converter using an amplifier preset technique,” in International Solid-State Circuits Conference, 2004, pp. 254–255.
[120] Taft, R. C., Menkus, C. A., Tursi, M. R., Hidri, O., and Pons, V., “Advances in high-speed ADC architectures using offset calibration,” in Analog Circuit Design: High-Speed AD Converters, Automotive Electronics and Ultra-Low Power Wireless, Roermund, A. H. M., Casier, H., and Steyaert, M., Eds. Kluwer, Dordrecht, the Netherlands, 2006, pp. 189–210.
[121] Vorenkamp, P. and Roovers, R., “A 12-b, 60-MSample/s cascaded folding and interpolating ADC,” IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1876–1886, 1997.
[122] Choe, M.-J., Song, B.-S., and Bacrania, K., “An 8-b 100-MSample/s CMOS pipelined folding ADC,” IEEE International Journal of Solid State Circuits, vol. 36, no. 2, pp. 184–194, 2001.
[123] Nakajima, Y., Sakaguchi, A., Ohkido, T., Matsumoto, T., and Yotsuyanagi, M., “A selfbackground calibrated 6 b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture,” in VLSI Circuits Conference, 2007, pp. 266–267.
[124] Nakajima, Y., Sakaguchi, A., Ohkido, T., Matsumoto, T., and Yotsuyanagi, M., “A background self-calibrated 6 b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture,” IEEE International Journal of Solid State Circuits, vol. 45, no. 4, pp. 707–718, 2010.
[125] Bogue, I. and Flynn, M. P., “A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS,” in Custom Integrated Circuits Conference, 2007, pp. 337–340.
[126] Makigawa, K., Ono, K., Ohkawa, T., Matsuura, K., and Segami, M., “A 7 bit 800 Msps 120mW folding and interpolation ADC using a mixed-averaging scheme,” in VLSI Circuits Conference, 2006, pp. 138–139.
[127] Razzaghi, A., Tam, S.-W., Kalkhoran, P.et al., “A single-channel 10 b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding,” in Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, pp. 265–266.
[128] Chen, Y., Huang, Q., and Burger, T., “A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS,” in European Solid-State Circuits Conference, 2007, pp. 155–158.
[129] Taft, R. C., Francese, P. A., Tursi, M. R.et al., “A 1.8 V 1.0 GS/s 10 b self-calibrating unifiedfolding-interpolating ADC with 9.1 ENOB at Nyquist frequency,” IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3294–3304, 2009.
[130] Plas, G., Decoutere, S., and Donnay, S., “A 0.16 pJ/conversion-step 2.5mW1.25 GS/s 4 b ADC in a 90 nm digital CMOS process,” in International Solid-State Circuits Conference, 2006, pp. 566–567.
[131] Sayiner, N., Sorensen, H., and Viswanathan, T., “A new signal acquisition technique,” in IEEE International Symposium on Circuits and Systems, 1992, pp. 1140–1143.
[132] Sayiner, N., Sorensen, H., and Viswanathan, T., “A level-crossing sampling scheme for A/D conversion,” IEEE Transactions on Circuits and Systems – Part II, vol. 43, no. 4, pp. 335–339, 1996.
[133] Tsividis, Y., “Event-driven data acquisition and digital signal processing – a tutorial,” IEEE Transactions on Circuits and Systems – Part II, vol. 57, no. 8, pp. 577–581, 2010.
[134] Tsividis, Y., “Event-driven data acquisition and continuous-time digital signal processing,” in Custom Integrated Circuits Conference, 2010, pp. 1–8.
[135] Tsividis, Y., “Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity,” in IEEE International Symposium on Circuits and Systems, 2010, pp. 3581–3584.
[136] Burrus, C. S., Gopinath, R. A., and Guo, H., Introduction to Wavelets and Wavelet Transforms: A Primer. Prentice Hall, New York, NY, 1998.
[137] Russell, G., Kinniment, D. J., Chester, E. G., and McLauchlan, M. R., CAD for VLSI. Van Nostrand Reinhold, London, UK, 1985.
[138] White, J. K. and Sangiovanni-Vincentelli, A., Relaxation Techniques for the Simulation of VLSI Circuits. Kluwer, Dordrecht, the Netherlands, 1987.
[139] Ellis, P. H., “Extension of phase plane analysis to quantized systems,” IRE Transactions on Automatic Control, vol. 4, no. 2, pp. 43–54, 1959.
[140] Dorf, R. C., Farren, M. C., and Phillips, C. A., “Adaptive sampling frequency for sampleddata control systems,” IRE Transactions on Automatic Control, vol. 7, no. 1, pp. 38–47, 1962.
[141] Donoho, D., “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, no. 4, pp. 1289–1306, 2006.
[142] Trakimas, M. and Sonkusale, S. R., “An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications,” IEEE Transactions on Circuits and Systems – Part I, vol. 58, 2011.
[143] Akopyan, F., Manohar, R., and Apsel, A. B., “A level-crossing flash asynchronous analog-todigital converter,” in IEEE International Symposium on Asynchronous Circuits and Systems, 2006, pp. 12–22.
[144] Schell, B. and Tsividis, Y., “A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation,” IEEE International Journal of Solid State Circuits, vol. 43, no. 11, pp. 2472–2481, 2008.
[145] Trakimas, M. and Sonkusale, S. R., “A 0.8 V asynchronous ADC for energy constrained sensing applications,” in Custom Integrated Circuits Conference, 2008, pp. 173–176.
[146] Kurchuk, M. and Tsividis, Y., “Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing,” IEEE Transactions on Circuits and Systems – Part I, vol. 57, no. 5, pp. 982–991, 2010.
[147] Schelleng, J. C., “Code modulation communication system,” US Patent 2 453 461, 1948.
[148] Gordon, B. M. and Colton, E. T., “Signal conversion apparatus,” US Patent 2 997 704, 1961.
[149] Baschirotto, A., “ISSCC 2009 tutorial succesive approximation register (SAR) A/D converters,” in International Solid-State Circuits Conference, IEEE, 2009.
[150] McCreary, J. L. and Gray, P. R., “All-MOS charge redistribution analog-to-digital conversion techniques, part I,” IEEE International Journal of Solid State Circuits, vol. 10, no. 6, pp. 371–379, 1975.
[151] Kuttner, F., “A 1.2V 10 b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS,” in International Solid-State Circuits Conference, 2002, pp. 136–137.
[152] Confalonieri, P., Zamprogno, M., Girardi, F., Nicollini, G., and Nagari, A., “A 2.7mW lMSPS 10 b analog-to-digital converter with built-in reference buffer and l LSB accuracy programmable input ranges,” in European Solid-State Circuits Conference, 2004, pp. 255–258.
[153] Craninckx, J. and Plas, G., “A 65 fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” in International Solid-State Circuits Conference, 2007, pp. 246–247.
[154] Manganaro, G., Kwak, S.-U., and Bugeja, A., “A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer,” IEEE International Journal of Solid State Circuits, vol. 39, no. 11, pp. 1829–1838, 2004.
[155] Lewis, S. H., Fetterman, H. S., Gross, G. F. Jr., Ramachandran, R., and Viswanathan, T. R., “A 10-b 20-Msample/s analog-to-digital converter,” IEEE International Journal of Solid State Circuits, vol. 27, no. 3, pp. 351–358, 1992.
[156] Giannini, V., Nuzzo, P., Chironi, V.et al., “An 820 μW 9 b 40MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,” in International Solid-State Circuits Conference, 2008, pp. 238–239.
[157] Chen, S.-W. M. and Brodersen, R. W., “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS,” IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2669–2680, 2006.
[158] Ginsburg, B. P. and Chandrakasan, A. P., “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2005, pp. 184–187.
[159] Ginsburg, B. P. and Chandrakasan, A. P., “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE International Journal of Solid State Circuits, vol. 42, no. 4, pp. 739–747, 2007.
[160] Elzakker, M., Tuijl, E., Geraedts, P.et al., “A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s,” IEEE International Journal of Solid State Circuits, vol. 45, no. 5, pp. 1007–1015, 2010.
[161] Svensson, L. J. and Koller, J. G., “Driving a capacitive load without dissipating fCV2,” in IEEE Symposium on Low Power Electronics, 1994, pp. 100–101.
[162] Draxelmayr, D., “A 6 b 600MHz 10mW ADC array in digital 90 nm CMOS,” in International Solid-State Circuits Conference, 2004, pp. 264–265.
[163] Ginsburg, B. P. and Chandrakasan, A. P., “Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS,” IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2641–2650, 2008.
[164] McNeill, J., Coln, M. C. W., and Larivee, B. J., “‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE International Journal of Solid State Circuits, vol. 40, no. 12, pp. 2437–2445, 2005.
[165] Plas, G. and Verbruggen, B., “A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS,” IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2631–2640, 2008.
[166] Hurrell, C. P., Lyden, C., Laing, D., Hummerston, D., and Vickery, M., “An 18 b 12.5 MS/s ADC with 93 dB SNR,” IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2647–2654, 2010.
[167] Wei, H., Chan, C.-H., Chio, U.-F.et al., “A 0.024mm2 8 b 400 MS/s SAR ADC with 2 b/cycle and resistive DAC in 65 nm CMOS,” in International Solid-State Circuits Conference, 2011, pp. 187–188.
[168] Deloraine, E. M., Mierlo, S., and Derjavitch, B., “Méthode et système de transmission par impulsions,” French Patent 932 140, 1946.
[169] Deloraine, E. M., Mierlo, S., and Derjavitch, B., “Communication system utilizing constant amplitude pulses of opposite polarities,” US Patent 2 629 857, 1953.
[170] Jager, F., “Delta modulation: A method of PCM transmission using the one unit code,” Phillips Research Report, vol. 7, pp. 542–546, 1952.
[171] Weg, H., “Quantizing noise of a single integration delta modulation system with an N-digit code,” Phillips Research Report, vol. 8, pp. 367–385, 1953.
[172] Cutler, C. C., “Differential quantization of communication signals,” US Patent 2 605 361, 1952.
[173] Cutler, C. C., “Transmission systems employing quantization,” US Patent 2 927 962, 1960.
[174] Inose, H., Yasuda, Y., and Murakami, J., “A telemetering system by code modulation – Δ–∑ modulation,” IRE Transactions on Space Electronics and Telemetry, vol. 8, no. 9, pp. 204–209, 1962.
[175] Norsworthy, S. R., Schreier, R., and Temes, G. C., Eds., Delta–Sigma Data Converters: Theory, Design and Simulation. IEEE Press, Piscataway, NJ, 1996.
[176] Pavan, S., “Alias rejection of continuous-time Δ∑ modulators with switched-capacitor feedback DACs,” IEEE Transactions on Circuits and Systems – Part I, vol. 58, no. 2, pp. 233–243, 2011.
[177] Bolatkale, M., Breems, L. J., Rutten, R., and Makinwa, K. A., “A 4 GHz CT ADC with 70 dB DR and 74 dBFS THD in 125MHz BW,” in International Solid-State Circuits Conference, 2011, pp. 470–471.
[178] Mitteregger, G., Ebner, C., Mechnig, S.et al., “A 20-mW 640-MHz CMOS continuous-time ∑Δ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2641–2649, 2006.
[179] Veldhoven, R. H., Rutten, R., and Breems, L. J., “An inverter-based hybrid Δ∑ modulator,” in International Solid-State Circuits Conference, 2008, pp. 492–493.
[180] Patón, S., Giandomenico, A. Di, Hernández, L.et al., “A 70-mW 300-MHz CMOS continuous-time ∑Δ ADC with 15-MHz bandwidth and 11 bits of resolution,” IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1056–1063, 2004.
[181] Keller, M., Buhmann, A., Sauerbrey, J., Ortmanns, M., and Manoli, Y., “Acomparative study on excess-loop-delay compensation techniques for continuous-time sigma–delta modulators,” IEEE Transactions on Circuits and Systems – Part I, vol. 55, no. 11, pp. 3480–3487, 2008.
[182] Nguyen, K., Adams, R., Sweetland, K., and Chen, H., “A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio,” IEEE International Journal of Solid State Circuits, vol. 40, no. 12, pp. 2408–2415, 2005.
[183] Morrow, P., Chamarro, M., Lyden, C.et al., “A 0.18 μm 102 dB-SNR mixed CT SC audioband ADC,” in International Solid-State Circuits Conference, 2005, pp. 178–179.
[184] Dörrer, L., Kuttner, F., Santner, A.et al., “A 2.2 mW, continuous-time Sigma–Delta ADC for voice coding with 95 dB dynamic range in a 65 nm CMOS process,” in European Solid-State Circuits Conference, 2006, pp. 195–198.
[185] Dörrer, L., Kuttner, F., Santner, A.et al., “A continuous time Δ∑ ADC for voice coding with 92 dB DR in 45 nm CMOS,” in International Solid-State Circuits Conference, 2008, pp. 502–503.
[186] Galton, I., “Delta–sigma data conversion in wireless transceivers,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 303–315, 2002.
[187] Raghavan, G., Jensen, J. F., Laskowski, J.et al., “Architecture, design, and test of continuoustime tunable intermediate-frequency bandpass delta–sigma modulators,” IEEE International Journal of Solid State Circuits, vol. 36, no. 1, pp. 5–13, 2001.
[188] Schreier, R., Lloyd, J., Singer, L.et al.., “A 10–300-MHz IF-digitizing IC with 90–105-dB dynamic range and 15–333-kHz bandwidth,” IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1636–1644, 2002.
[189] Schreier, R., Abaskharoun, N., Shibata, H.et al., “A 375-mW quadrature bandpass Δ∑ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz,” IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2632–2640, 2006.
[190] Breems, L. J., Rutten, R., Veldhoven, R. H. M., and Weide, G., “A 56 mW continuous-time quadrature cascaded Δ∑ modulator with 77 dB DR in a near zero-IF 20 MHz band,” IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2696–2705, 2007.
[191] Silva, P. G. R., Breems, L. J., Makinwa, K. A. A., Roovers, M. Raf, and Huijsing, J. H., “An IF-to-baseband ∑Δ modulator for AM/FM/IBOC radio receivers with a 118 dB dynamic range,” IEEE International Journal of Solid State Circuits, vol. 42, no. 5, pp. 1076–1089, 2007.
[192] Thandri, B. K. and Silva-Martinez, J., “A 63 dB SNR, 75-mW bandpass RF ∑Δ ADC at 950 MHz using 3.8-GHz clock in 0.25-μm SiGe BiCMOS technology,” IEEE International Journal of Solid State Circuits, vol. 42, no. 2, pp. 269–279, 2007.
[193] Yang, W., Schofield, W., Shibata, H.et al., “A 100mW 10 MHz-BW CT modulator with 87 dB DR and 91 dBc IMD,” in International Solid-State Circuits Conference, 2008, pp. 498–499.
[194] Carley, L. R., “A noise-shaping coder topology for 15 + bit converters,” IEEE International Journal of Solid State Circuits, vol. 24, no. 2, pp. 267–273, 1989.
[195] Baird, R. T. and Fiez, T. S., “Linearity enhancement of multibit ∑Δ A/D and D/A converters using data weighted averaging,” IEEE Transactions on Circuits and Systems – Part II, vol. 42, no. 12, pp. 753–762, 1995.
[196] Radke, R. E., Eshraghi, A., and Fiez, T. S., “A 14-bit current-mode Δ∑ DAC based upon rotated data weighted averaging,” IEEE International Journal of Solid State Circuits, vol. 35, no. 8, pp. 1074–1084, 2000.
[197] Chen, F. and Leung, B. H., “A high resolution multibit sigma – delta modulator with individual level averaging,” IEEE International Journal of Solid State Circuits, vol. 30, no. 4, pp. 453–460, 1995.
[198] Hamoui, A. A. and Martin, K. W., “High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling Δ∑ ADCs for broad-band applications,” IEEE Transactions on Circuits and Systems – Part I, vol. 51, no. 1, pp. 72–85, 2004.
[199] Lee, D.-H., Lin, Y.-H., and Kuo, T.-H., “Nyquist-rate current-steering digital-to-analog converters with random multiple data-weighted averaging technique and QN rotated walk switching scheme,” IEEE Transactions on Circuits and Systems – Part II, vol. 53, no. 11, pp. 1264–1268, 2006.
[200] Huang, S.-J. and Lin, Y.-Y., “A 1.2V 2MHz BW 0.084mm2 CT Δ∑ ADC with -97.7 dBc THD and 80 dB DR using low-latency DEM,” in International Solid-State Circuits Conference, 2009, pp. 172–173.
[201] Ryckaert, J., Borremans, J., Verbruggen, B.et al., “A 2.4 GHz low-power sixth-order RF bandpass Δ∑ converter in CMOS,” IEEE International Journal of Solid State Circuits, vol. 44, no. 11, pp. 2873–2880, 2009.
[202] Galdi, I., Bonizzoni, E., Malcovati, P., Manganaro, G., and Maloberti, F., “40 MHz IF 1 MHz bandwidth two-path bandpass ∑Δ modulator with 72 dB DR consuming 16 mW,” IEEE International Journal of Solid State Circuits, vol. 43, no. 7, pp. 1648–1656, 2008.
[203] Lyden, C., Ryan, J., Ugarte, C. A., Kornblum, J., and Yung, F. M., “A single shot sigma delta analog to digital converter for multiplexed applications,” in Custom Integrated Circuits Conference, 1995, pp. 203–206.
[204] Holloway, P. R., Blom, E. D., Wan, J., and Urie, S. H., “Digitizing temperature measurement system and method of operation,” US Patent 6 962 436, 2005.
[205] Jansson, C., “A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS,” IEEE Transactions on Circuits and Systems – Part I, vol. 42, no. 11, pp. 904–912, 1995.
[206] Harjani, R. and Lee, T. A., “FRC: A method for extending the resolution of Nyquist rate converters using oversampling,” IEEE Transactions on Circuits and Systems – Part II, vol. 45, no. 4, pp. 482–494, 1998.
[207] Rombouts, P., Wilde, W. D., and Weyten, L., “A 13.5-b 1.2-V micropower extended counting A/D converter,” IEEE International Journal of Solid State Circuits, vol. 36, no. 2, pp. 176–183, 2001.
[208] Schott, C., Racz, R., Manco, A., and Simonne, N., “CMOS single-chip electronic compass with microcontroller,” IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2923–2933, 2007.
[209] Lee, H.-S., Brooks, L., and Sodini, C. G., “Zero-crossing-based ultra-low-power A/D converters,” Proceedings of the IEEE, vol. 98, no. 2, pp. 315–332, 2010.
[210] Fiorenza, J. K., Sepke, T., Holloway, P., Sodini, C. G., and Lee, H.-S., “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2658–2668, 2006.
[211] Brooks, L. and Lee, H.-S., “A zero-crossing-based 8-bit 200 MS/s pipelined ADC,” IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2677–2687, 2007.
[212] Shin, S.-K., You, Y.-S., Lee, S.-H.et al., “A fully-differential zero-crossing-based 1.2 V 10 b 26 MS/s pipelined ADC in 65 nm CMOS,” in VLSI Circuits Conference, 2008, pp. 218–219.
[213] Musah, T., Kwon, S., Lakdawala, H., Soumyanath, K., and Moon, U.-K., “A 630 μW zero-crossing-based Δ∑ ADC using switched-resistor current sources in 45 nm CMOS,” in Custom Integrated Circuits Conference, 2009, pp. 1–4.
[214] Brooks, L. and Lee, H.-S., “A 12 b, 50 MS/s, fully differential zero-crossing based pipelined ADC,” IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3329–3343, 2009.
[215] Brooks, L. and Lee, H.-S., “Background calibration of pipelined ADCs via decision boundary gap estimation,” IEEE Transactions on Circuits and Systems – Part I, vol. 55, no. 10, pp. 2969–2979, 2008.
[216] Sepke, T., Holloway, P., Sodini, C. G., and Lee, H.-S., “Noise analysis for comparator-based circuits,” IEEE Transactions on Circuits and Systems – Part I, vol. 56, no. 3, pp. 541–553, 2009.
[217] Gregoire, B. R. and Moon, U.-K., “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain,” IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2620–2630, 2008.
[218] Nagaraj, K., “Switched-capacitor circuits with reduced sensitivity to amplifier gain,” IEEE Transactions on Circuits and Systems, vol. 34, no. 5, pp. 571–574, 1987.
[219] Hershberg, B., Weaver, S., and Moon, U.-K., “Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp,” IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2623–2633, 2010.
[220] Veillette, B. R. and Roberts, G. W., “High frequency sinusoidal generation using delta–sigma modulation techniques,” in IEEE International Symposium on Circuits and Systems, 1995, pp. 637–640.
[221] Roza, E., “Analog-to-digital conversion via duty-cycle modulation,” IEEE Transactions on Circuits and Systems – Part II, vol. 44, no. 11, pp. 907–914, 1997.
[222] Santos, D., Dow, S., Flasck, J., and Levi, M., “A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip,” IEEE Transactions on Nuclear Science, vol. 43, no. 3, pp. 1717–1727, 1996.
[223] Roberts, G. W. and Ali-Bakhshian, M., “A brief introduction to time-to-digital and digital-to-time converters,” IEEE Transactions on Circuits and Systems – Part II, vol. 57, no. 3, pp. 153–157, 2010.
[224] Best, R. E., Ed., Phase-Locked Loops: Design, Simulation and Applications, 4th edn. McGraw-Hill, New York, NY, 1999.
[225] Dudek, P., Szczepański, S., and Hatfield, J. V., “A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line,” IEEE International Journal of Solid State Circuits, vol. 35, no. 2, pp. 240–247, 2000.
[226] Sidiropoulos, S. and Horowitz, M. A., “A semidigital dual delay-locked loop,” IEEE International Journal of Solid State Circuits, vol. 32, no. 11, pp. 1683–1692, 1997.
[227] Hanumolu, P. K., Kratyuk, V., Wei, G.-Y., and Moon, U.-K., “A sub-picosecond resolution 0.5–1.5 GHz digital-to-phase converter,” IEEE International Journal of Solid State Circuits, vol. 43, no. 2, pp. 414–424, 2008.
[228] Iwata, A., Sakimura, N., Nagata, M., and Morie, T., “The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer,” IEEE Transactions on Circuits and Systems – Part II, vol. 46, no. 7, pp. 941–945, 1999.
[229] Yoon, Y.-G., Kim, J., Jang, T.-K., and Cho, S., “A time-based bandpass ADC using time-interleaved voltage-controlled oscillators,” IEEE Transactions on Circuits and Systems – Part I, vol. 55, no. 11, pp. 3571–3581, 2008.
[230] Høvin, M., Olsen, A., Lande, T. S., and Toumazou, C., “A mostly-digital variable-rate continuous-time delta–sigma modulator ADC,” IEEE International Journal of Solid State Circuits, vol. 32, no. 1, pp. 13–22, 1997.
[231] Straayer, M. Z. and Perrott, M. H., “A 12-bit, 10-MHz bandwidth, continuous-time ∑Δ ADC with a 5-bit, 950-MS/s VCO-based quantizer,” IEEE International Journal of Solid State Circuits, vol. 43, no. 4, pp. 805–814, 2008.
[232] Wulff, C. and Ytterdal, T., “Resonators in open-loop sigma–delta modulators,” IEEE Transactions on Circuits and Systems – Part I, vol. 56, no. 10, pp. 2159–2172, 2009.
[233] Yoon, Y.-G. and Cho, S., “A 1.5-GHz 63 dB SNR 20 mW direct RF sampling bandpass VCO-based ADC in 65 nm CMOS,” in VLSI Circuits Conference, 2009, pp. 270–271.
[234] Kim, J., Jang, T.-K., Yoon, Y.-G., and Cho, S., “Analysis and design of voltage-controlled oscillator based analog-to-digital converter,” IEEE Transactions on Circuits and Systems – Part I, vol. 57, no. 1, pp. 18–30, 2010.
[235] Taylor, G. and Galton, I., “A mostly-digital variable-rate continuous-time delta–sigma modulator ADC,” IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2634–2646, 2010.
[236] Park, M. and Perrott, M. H., “A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time Δ∑ ADC with VCO-based integrator and quantizer implemented in 0.13 μ CMOS,” IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3344–3358, 2009.
[237] Agnes, A., Bonizzoni, E., Malcovati, P., and Maloberti, F., “A 9.4-ENOB 1V 3.8 μW 100 kS/s SAR ADC with time-domain comparator,” in International Solid-State Circuits Conference, 2008, pp. 246–247.
[238] Naraghi, S., Courcy, M., and Flynn, M. P., “A 9-bit, 14 μw and 0.06 mm2 pulse position modulation ADC in 90 nm digital CMOS,” IEEE International Journal of Solid State Circuits, vol. 45, no. 9, pp. 1870–1880, 2010.
[239] Robertson, D., “The past, present, and future of data converters and mixed signal ICs: A ‘universal’ model,” in VLSI Circuits Conference, 2006, pp. 1–4.
[240] Murmann, B. and Boser, B. E., “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE International Journal of Solid State Circuits, vol. 38, no. 12, pp. 2040–2050, 2003.
[241] Yang, W., Kelly, D., Mehr, I., Sayuk, M. T., and Singer, L., “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,” IEEE International Journal of Solid State Circuits, vol. 36, no. 12, pp. 1931–1936, 2001.
[242] Abidi, A. A., Matsuzawa, A., Staszewski, B.et al., “A-SSCC 2008 panel on digitally assisted analog and RF circuits: Potentials and issues,” in IEEE Asian Solid-State Circuits Conference, IEEE, 2008.
[243] Baschirotto, A., “ISSCC 2008 forum on digitally-assisted analog & RF circuits,” in International Solid-State Circuits Conference, IEEE, 2008.
[244] Li, J. and Moon, U.-K., “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Transactions on Circuits and Systems – Part II, vol. 50, no. 9, pp. 531–538, 2003.
[245] Siragusa, E. and Galton, I., “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE International Journal of Solid State Circuits, vol. 39, no. 12, pp. 2126–2138, 2004.
[246] Chiu, Y., Tsang, C. W., Nikolić, B., and Gray, P. R., “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE Transactions on Circuits and Systems – Part I, vol. 51, no. 1, pp. 38–46, 2004.
[247] Keane, J. P., Hurst, P. J., and Lewis, S. H., “Background interstage gain calibration technique for pipelined ADCs,” IEEE Transactions on Circuits and Systems – Part I, vol. 52, no. 1, pp. 32–43, 2005.
[248] Keane, J. P., Hurst, P. J., and Lewis, S. H., “Digital background calibration for memory effects in pipelined analog-to-digital converters,” IEEE Transactions on Circuits and Systems – Part I, vol. 53, no. 3, pp. 511–525, 2006.
[249] Heinen, S. and Leenaerts, D., “ISSCC 2010 forumon reconfigurable RF and data converters,” in International Solid-State Circuits Conference, IEEE, 2010.
[250] Crombez, P., Plas, G., Steyaert, M. S. J., and Craninckx, J., “A single-bit 500 kHz–10 MHz multimode power-performance scalable 83-to-67 dB DR CT Δ∑ for SDR in 90 nm digital CMOS,” IEEE International Journal of Solid State Circuits, vol. 45, no. 6, pp. 1159–1171, 2010.
[251] Malla, P., Lakdawala, H., Kornegay, K., and Soumyanath, K., “A 28mW spectrum-sensing reconfigurable 20 MHz 72 dB-SNR 70 dB-SNDR DT ADC for 802.11n/WiMAX receivers,” in International Solid-State Circuits Conference, 2008, pp. 496–497.
[252] Oh, Y. and Murmann, B., “A low-power, 6-bit time-interleaved SAR ADC using OFDM pilot tone calibration,” in Custom Integrated Circuits Conference, 2007, pp. 193–196.
[253] Brooks, T. L., Robertson, D. H., Kelly, D. F., Muro, A. Del, and Harston, S. W., “A cascaded sigma–delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR,” IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1896–1906, 1997.
[254] Verbruggen, B., Craninckx, J., Kuijk, M., Wambacq, P., and Plas, G., “A 2.2 mW 5 b 1.75 GS/s folding flash ADC in 90 nm digital CMOS,” in International Solid-State Circuits Conference, 2008, pp. 252–253.
[255] Verbruggen, R., Craninckx, J., Kuijk, M., Wambacq, P., and Plas, G., “A 2.6 mW 6 b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS,” in International Solid-State Circuits Conference, 2010, pp. 296–297.
[256] Black, W. C. Jr. and Hodges, D. A., “Time interleaved converter arrays,” IEEE International Journal of Solid State Circuits, vol. 15, no. 6, pp. 1022–1029, 1980.
[257] Doris, K., Janssen, E., Nani, C., Zanikopoulos, A., and Weide, G., “A 480 mW 2.6 GS/s 10 b 65 nm CMOS time-interleaved ADC with 48.5 db SNDR up to Nyquist,” in International Solid-State Circuits Conference, 2011, pp. 180–181.
[258] Petraglia, A. and Mitra, S. K., “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer,” IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 5, pp. 831–835, 1991.
[259] Kurosawa, N., Kobayashi, H., Maruyama, K., Sugawara, H., and Kobayashi, K., “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Transactions on Circuits and Systems – Part I, vol. 48, no. 3, pp. 261–271, 2001.
[260] Vogel, C., “The impact of combined channel mismatch effects in time-interleaved ADCs,” IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 1, pp. 415–427, 2005.
[261] Fu, D., Dyer, K. C., Lewis, S. H., and Hurst, P. J., “A digital background calibration technique for time-interleaved analog-to-digital converters,” IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1904–1911, 1998.
[262] Dyer, K. C., Fu, D., Lewis, S. H., and Hurst, P. J., “An analog background calibration technique for time-interleaved analog-to-digital converters,” IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1912–1919, 1998.
[263] Tsai, T.-H., Hurst, P. J., and Lewis, S. H., “Bandwidth mismatch and its correction in time-interleaved analog-to-digital converters,” IEEE Transactions on Circuits and Systems – Part II, vol. 53, no. 10, pp. 1133–1137, 2006.
[264] Jamal, S. M., Fu, D., Chang, N. C.-J., Hurst, P. J., and Lewis, S. H., “A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration,” IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1618–1627, 2002.
[265] Mulder, J., Goes, F. M., Vecchi, D.et al., “An 800 MS/s dual-residue pipeline ADC in 40 nm CMOS,” in International Solid-State Circuits Conference, 2011, pp. 184–185.
[266] Kim, K. Y., Kusayanagi, N., and Abidi, A. A., “A 10-b, 100-MS/s CMOS A/D converter,” IEEE International Journal of Solid State Circuits, vol. 32, no. 3, pp. 302–311, 1997.
[267] Jin, H. and Lee, E. K. F., “A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs,” IEEE Transactions on Circuits and Systems – Part II, vol. 47, no. 7, pp. 603–613, 2000.
[268] Camarero, D., Kalaia, K. B., Naviner, J.-F., and Loumeau, P., “Mixed-signal clock-skew calibration technique for time-interleaved ADCs,” IEEE Transactions on Circuits and Systems – Part I, vol. 55, no. 11, pp. 3676–3687, 2008.
[269] Elbornsson, J. and Eklund, J.-E., “Blind estimation of timing errors in interleaved A/D converters,” in IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 6, 2001, pp. 3913–3917.
[270] Elbornsson, J., Gustafsson, F., and Eklund, J.-E., “Blind equalization of time errors in a time-interleaved ADC system,” IEEE Transactions on Signal Processing, vol. 53, no. 4, pp. 1413–1424, 2005.
[271] Waltari, M. and Halonen, K., “Timing skew insensitive switching for double sampled circuits,” in IEEE International Symposium on Circuits and Systems, vol. 1, 1999, pp. 61–64.
[272] Gustavsson, M. and Tan, N. N., “Explicit analysis of channel mismatch effects in timeinterleaved ADC systems,” IEEE Transactions on Circuits and Systems – Part II, vol. 47, no. 9, pp. 821–831, 2000.
[273] Manganaro, G., “Feed-forward approach for timing skew in interleaved and double-sampled circuits,” US Patent 6542017, 2003.
[274] Gupta, S. K., Inerfield, M. A., and Wang, J., “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2650–2657, 2006.
[275] Greshishchev, Y. M., Aguirre, J., Besson, M.et al., “A 40GS/s 6 b ADC in 65 nm CMOS,” in International Solid-State Circuits Conference, 2010, pp. 390–391.
[276] Poulton, K., Knudsen, K. L., Kerley, J.et al., “An 8-GSa/s 8-bit ADC system,” in VLSI Circuits Conference, 1997, pp. 23–24.
[277] Tamba, M., Shimizu, A., Munakata, H., and Komuro, T., “A method to improve SFDR with random interleaved sampling method,” in IEEE International Test Conference, 2001, pp. 512–520.
[278] Bernardinis, G., Malcovati, P., Maloberti, F., and Soenen, E., “Dynamic stage matching for parallel pipeline A/D converters,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2002, pp. 905–909.
[279] El-Sankary, K., Assi, A., and Sawan, M., “New sampling method to improve the SFDR of time-interleaved ADCs,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2003, pp. 833–836.
[280] Elbornsson, J., Gustafsson, F., and Eklund, J.-E., “Analysis of mismatch effects in a randomly interleaved A/D converter system,” IEEE Transactions on Circuits and Systems – Part I, vol. 52, no. 3, pp. 465–476, 2005.
[281] Galton, I., “Digital cancellation of D/A converter noise in pipelined A/D converters,” IEEE Transactions on Circuits and Systems – Part II, vol. 47, no. 3, pp. 185–196, 2000.
[282] Siragusa, E. J. and Galton, I., “Gain error correction technique for pipelined analogue-todigital converters,” IEE Electronics Letters, vol. 36, no. 7, pp. 617–618, 2000.
[283] Wang, X., Hurst, P. J., and Lewis, S. H., “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE International Journal of Solid State Circuits, vol. 39, no. 9, pp. 1799–1808, 2004.
[284] Grace, C. R., Hurst, P. J., and Lewis, S. H., “A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration,” IEEE International Journal of Solid State Circuits, vol. 40, no. 5, pp. 1038–1046, 2005.
[285] Sun, N., Lee, H.-S., and Ham, D., “Digital background calibration in pipelined ADCs using commutated feedback capacitor switching,” IEEE Transactions on Circuits and Systems – Part II, vol. 55, no. 9, pp. 877–881, 2008.
[286] Wang, H., Wang, X., Hurst, P. J., and Lewis, S. H., “Nested digital background calibration of a 12-bit pipelined ADC without an input SHA,” IEEE International Journal of Solid State Circuits, vol. 44, no. 10, pp. 2780–2789, 2009.
[287] Mehr, I. and Singer, L., “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,” IEEE International Journal of Solid State Circuits, vol. 35, no. 3, pp. 318–325, 2000.
[288] Chang, D.-Y., “Design techniques for a pipelined ADC without using a front-end sampleand- hold amplifier,” IEEE Transactions on Circuits and Systems – Part I, vol. 51, no. 11, pp. 2123–2132, 2004.
[289] Yoshioka, M., Kudo, M., Gotoh, K., and Watanabe, Y., “A 10 b 125 MS/s 40mW pipelined ADC in 0.18 μmCMOS,” in International Solid-State Circuits Conference, 2005, pp. 282–283.
[290] Jeon, Y.-D., Lee, S.-C., Kim, K.-D., Kwon, J.-K., and Kim, J., “A 4.7mW 0.32mm2 10 b 30 MS/s pipelined ADC without a front-end S/H in 90 nm CMOS,” in International Solid- State Circuits Conference, 2007, pp. 456–457.
[291] Lee, B.-G., Min, B.-M., Manganaro, G., and Valvano, J.W., “A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC,” IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2613–2619, 2008.
[292] Min, B.-M., Kim, P., Bowman, F. W. III, Boisvert, D. M., and Aude, A. J., “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE International Journal of Solid State Circuits, vol. 38, no. 12, pp. 2031–2039, 2003.
[293] Yoshioka, M., Kudo, M., Gotoh, K., and Watanabe, Y., “A 1.8 v 10 b 210 MS/sCMOS pipelined ADC featuring 86 dB SFDR without calibration,” in Custom Integrated Circuits Conference, 2007, pp. 317–320.
[294] Gubbins, D., Lee, B., Hanumolu, P. K., and Moon, U.-K., “Continuous-time input pipeline ADCs,” IEEE International Journal of Solid State Circuits, vol. 45, no. 8, pp. 1456–1468, 2010.
[295] Bastiaansen, C. A. A., Groeneveld, D. W. J., Schouwenaars, H. J., and Termeer, H. A. H., “A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter,” IEEE International Journal of Solid State Circuits, vol. 26, no. 7, pp. 917–921, 1991.
[296] Toumazou, C., Hughes, J. B., and Battersby, N. C., Eds., Switched-Currents: An Analogue Technique for Digital Technology. Peter Peregrinus Ltd., on behalf of the IEE, London, UK, 1993.
[297] Bugeja, A. R., Song, B.-S., Rakers, P. L., and Gillig, S. F., “A 14-b, 100-MS/s CMOS DAC designed for spectral performance,” IEEE International Journal of Solid State Circuits, vol. 34, no. 12, pp. 1719–1732, 1999.
[298] Schofield, W., Mercer, D., and Onge, L. St., “A 16 b 400 MS/s DAC with < –80 dBc IMD to 300MHz and < –160 dBm/Hz noise power spectral density,” in International Solid-State Circuits Conference, 2003, pp. 126–127.
[299] Clara, M., Klatzer, W., Wiesbauer, A., and Straeussnigg, D., “A 350MHz low-OSR ΔΣ current-steering DAC with active termination in 0.13 μm CMOS,” in International Solid- State Circuits Conference, 2005, pp. 118–119.
[300] Nejati, B. and Larson, L., “An area optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC,” in Custom Integrated Circuits Conference, 2006, pp. 161–164.
[301] Jewett, B., Liu, J., and Poulton, K., “A 1.2 GS/s 15-bit DAC for precision signal generation,” in International Solid-State Circuits Conference, 2005, pp. 110–111.
[302] Choe, M.-J., Baek, K.-H., and Teshome, M., “A 1.6 GS/s 12 b return-to-zero GaAs RF DAC for multiple Nyquist operation,” in International Solid-State Circuits Conference, 2005, pp. 112–113.
[303] Schvan, P., Pollex, D., and Bellingrath, T., “A 22 GS/s 6 b DAC with integrated digital ramp generator,” in International Solid-State Circuits Conference, 2005, pp. 122–123.
[304] Baranauskas, D. and Zelenin, D., “A 0.36 W 6 b up to 20 GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference, 2006, pp. 580–581.
[305] Greenley, B., Veith, R., Chang, D.-Y., and Moon, U.-K., “A low-voltage 10-bit CMOS DAC in 0.01-mm2 die area,” IEEE Transactions on Circuits and Systems – Part II, vol. 52, no. 5, pp. 246–250, 2005.
[306] Lin, C.-H. and Bult, K., “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1948–1958, 1998.
[307] Radulov, G. I., Heydenreich, M., Hofstad, R. W., Hegt, J. A., and Roermund, A. H. M., “Brownian-bridge-based statistical analysis of the DAC INL caused by current mismatch,” IEEE Transactions on Circuits and Systems – Part II, vol. 54, no. 2, pp. 146–150, 2007.
[308] Luschas, S. and Lee, H.-S., “Output impedance requirements for DACs,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2003, pp. 861–864.
[309] Crippa, P., Turchetti, C., and Conti, M., “A statistical methodology for the design of highperformance CMOS current-steering digital-to-analog converters,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 377–394, 2002.
[310] Conroy, C. S. G., Lane, W. A., and Moran, M. A., “Statistical design techniques for D/A converters,” IEEE International Journal of Solid State Circuits, vol. 24, no. 4, pp. 1118–1128, 1989.
[311] Schafferer, B. and Adams, R., “A 3V CMOS 400mW 14 b 1.4 GS/s DAC for multicarrier applications,” in International Solid-State Circuits Conference, 2004, pp. 360–361.
[312] Plas, G. A. M., Vandenbussche, J., Sansen, W., Steyaert, M. S. J., and Gielen, G. G. E., “A 14-bit intrinsic accuracy q2 random walk CMOS DAC,” IEEE International Journal of Solid State Circuits, vol. 34, no. 12, pp. 1708–1718, 1999.
[313] Cong, Y. and Geiger, R. L., “Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays,” IEEE Transactions on Circuits and Systems – Part II, vol. 47, no. 7, pp. 585–595, 2000.
[314] Vadipour, M., “Gradient error cancellation and quadratic error reduction in unary and binary D/A converters,” IEEE Transactions on Circuits and Systems – Part II, vol. 50, no. 12, pp. 1002–1007, 2003.
[315] Manganaro, G. and Gyvez, J. Pineda, “A four quadrant S2 I switched-current multiplier,” IEEE Transactions on Circuits and Systems–Part II, vol. 45, no. 7, pp. 791–799, 1998.
[316] Bugeja, A. R. and Song, B.-S., “A self-trimming 14-b, 100-MS/s CMOS DAC,” IEEE International Journal of Solid State Circuits, vol. 35, no. 12, pp. 1841–1852, 2000.
[317] Huang, Q., Francese, P. A., Martelli, C., and Nielsen, J., “A 200 MS/s 14 b 97mW DAC in 0.18 μm CMOS,” in International Solid-State Circuits Conference, 2004, pp. 364–365.
[318] Manganaro, G., “Analog calibration of a current source array at low supply voltage,” US Patent 7161412, 2007.
[319] Manganaro, G., “Transresistance amplifier,” US Patent 7 202 744, 2007.
[320] Tang, Y., Briaire, J., Doris, K.et al., “A 14 b 200 MS/s DAC with SFDR > 78 dBc, IM3 < –83 dBc and NSD < –163 dBm/Hz across the whole Nyquist band enabled by dynamicmismatch mapping,” in VLSI Circuits Conference, 2010, pp. 151–152.
[321] Tseng, W.-H., Fan, C.-W., and Wu, J.-T., “A 12-bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz,” in International Solid-State Circuits Conference, 2011, pp. 192–193.
[322] Tseng, W.-H., Wu, J.-T., and Fan, C.-W., “A CMOS 8-bit 1.6 GS/s DAC with digital random return-to-zero,” IEEE Transactions on Circuits and Systems – Part II, vol. 58, no. 1, pp. 1–5, 2011.
[323] Hyde, J., Humes, T., Diorio, C., Thomas, M., and Figueroa, M., “A 300-MS/s 14-bit digital-to-analog converter in logic CMOS,” IEEE International Journal of Solid State Circuits, vol. 38, no. 5, pp. 734–740, 2003.
[324] Marche, D., Savaria, Y., and Gagnon, Y., “Laser fine-tuneable deep-submicrometer CMOS 14-bit DAC,” IEEE Transactions on Circuits and Systems – Part I, vol. 55, no. 8, pp. 2157–2165, 2008.
[325] Mercer, D. and Singer, L., “A 12-b 125 MSPS CMOS D/A designed for spectral performance,” in IEEE International Symposium on Low Power Electronics and Design, 1996, pp. 243–246.
[326] Bosch, A., Steyaert, M. S. J., and Sansen, W., “SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters,” in International Conference on Electronics, Circuits and Systems, vol. 3, 1999, pp. 1193–1196.
[327] Deveugele, J. and Steyaert, M. S. J., “RF DAC's: Output impedance and distortion,” in RF Circuits: Wide Band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage, Steyaert, M., Roermund, A., and Huijsing, J. H., Eds. Kluwer, Dordrecht, the Netherlands, 2006, pp. 45–64.
[328] Bosch, A., Steyaert, M., and Sansen, W. M., Static and Dynamic Performance Limitations for High Speed D/A Converters. Kluwer, Dordrecht, the Netherlands, 2004.
[329] Bosch, A., Borremans, M. A. F., Steyaert, M. S. J., and Sansen, W., “A 10-b, 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE International Journal of Solid State Circuits, vol. 36, no. 3, pp. 315–324, 2001.
[330] Bastos, J., Marques, A. M., Steyaert, M. S. J., and Sansen, W., “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1959–1969, 1998.
[331] Clara, M., Wiesbauer, A., and Klatzer, W., “Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2004, pp. 285–289.
[332] Manganaro, G., “Current steering digital to analog converter with improved dynamic linearity,” US Patent 7 023 367, 2006.
[333] Seo, D. and McAllister, G. H., “A low-spurious low-power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter,” IEEE International Journal of Solid State Circuits, vol. 42, no. 3, pp. 486–495, 2007.
[334] Doris, K., Briaire, J., Leenaerts, D., Vertregt, M., and Roermund, A., “A 12 b 500 MS/s DAC with > 70 dB SFDR up to 120MHz in 0.18 μm CMOS,” in International Solid-State Circuits Conference, 2005, pp. 116–117.
[335] Doris, K., Roermund, A. H. M., and Leenaerts, D., Wide-Bandwidth High Dynamic Range D/A Converters. Springer-Verlag, Berlin, Germany, 2010.
[336] Alioto, M. and Palumbo, G., Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Kluwer, Dordrecht, the Netherlands, 2010.
[337] Schafferer, B., “Control loop for minimal tailnode excursion of differential switches,” US Patent 6 774 683, 2004.
[338] Park, S., Kim, G., Park, S.-C., and Kim, W., “A digital-to-analog converter based on differential-quad switching,” IEEE International Journal of Solid State Circuits, vol. 37, no. 10, pp. 1335–1338, 2002.
[339] Schafferer, B., “Constant switching for signal processing,” US Patent 6 842 132, 2005.
[340] Hall, S. H., Hall, G. W., and McCall, J. A., High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices. John Wiley & Sons, New York, NY, 2000.
[341] Chen, T. and Gielen, G. G. E., “The analysis and improvement of a current-steering DACs dynamic SFDR – I: The cell-dependent delay differences,” IEEE Transactions on Circuits and Systems – Part I, vol. 53, no. 1, pp. 3–15, 2006.
[342] Chen, T. and Gielen, G. G. E., “The analysis and improvement of a current-steering DAC's dynamic SFDR – II: The output-dependent delay differences,” IEEE Transactions on Circuits and Systems – Part I, vol. 54, no. 2, pp. 268–279, 2007.
[343] Mercer, D., “Latch with data jitter free clock load,” US Patent 7 023 255, 2006.
[344] Mercer, D., “A low power current steering digital to analog converter in 0.18 micron CMOS,” in IEEE International Symposium on Low Power Electronics and Design, 2005, pp. 72–77.
[345] Bugeja, A. R., “High dynamic linearity current-mode digital-to-analog converter architecture,” US Patent 6 906 652, 2005.
[346] Gulati, K., Peng, M. S., Pulincherry, A.et al., “A highly integrated CMOS analog baseband transceiver with 180 MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs,” IEEE International Journal of Solid State Circuits, vol. 41, no. 8, pp. 1856–1866, 2006.
[347] Deveugele, J. and Steyaert, M. S. J., “A 10-b 250 MS/s binary-weighted current steering DAC,” IEEE International Journal of Solid State Circuits, vol. 41, no. 2, pp. 320–329, 2006.
[348] Wu, X., Palmers, P., and Steyaert, M. S. J., “A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC,” IEEE International Journal of Solid State Circuits, vol. 43, no. 11, pp. 2396–2403, 2008.
[349] Adams, R. W. and Nguyen, K. Q., “Dual return-to-zero pulse encoding in a DAC output stage,” US Patent 6 061 010, 1997.
[350] Adams, R., Nguyen, K. Q., and Sweetland, K., “A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling,” IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1871–1878, 1998.
[351] O'Sullivan, K., Gorman, C., Hennessy, M., and Callaghan, V., “A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44mm2,” IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1064–1072, 2004.
[352] Wu, X., Palmers, P., and Steyaert, M. S. J., “An 80-MHz 8-bit CMOS D/A converter,” IEEE International Journal of Solid State Circuits, vol. 21, no. 6, pp. 983–988, 1986.
[353] Kwan, T. W., Adams, R. W., and Libert, R., “A stereo multibit sigma delta DAC with asynchronous master-clock interface,” IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 1881–1887, 1996.
[354] Nguyen, K., Bandyopadhyay, A., Adams, R., Sweetland, K., and Baginski, P., “A 108 dB SNR 1.1 mW oversampling audio DAC with a three-level DEM technique,” IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2592–2600, 2008.
[355] Rombouts, P. and Weyten, L., “Dynamic element matching for pipelined A/D conversion,” in IEEE International Conference on Electronics, Circuits, and Systems, vol. 2, 1998, pp. 315–318.
[356] Chan, K. L., Zhu, J., and Galton, I., “Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs,” IEEE International Journal of Solid State Circuits, vol. 43, no. 9, pp. 2067–2078, 2008.
[357] Shui, T., Schreier, R., and Hudson, F., “Modified mismatch-shaping for continuous-time delta–sigma modulators,” in Custom Integrated Circuits Conference, 1998, pp. 225–228.
[358] Shui, T., Schreier, R., and Hudson, F., “Mismatch shaping for a current-mode multibit deltasigma DAC,IEEE International Journal of Solid State Circuits, vol. 34, no. 3, pp. 331–338, 1999.
[359] Fishov, A., Siragusa, E., Web, J., Fogleman, E., and Galton, I., “Segmented mismatch shaping D/A conversion,” in IEEE International Symposium on Circuits and Systems, vol. 4, 2002, pp. 679–682.
[360] Nordick, B., Petrie, C., and Cheng, Y., “Dynamic element matching techniques for deltasigma ADCs with large internal quantizers,” in IEEE International Symposium on Circuits and Systems, vol. 1, 2004, pp. 653–656.
[361] Cheng, Y., Petrie, C., Nordick, B., and Comer, D., “Multibit delta–sigma modulator with two-step quantization and segmented DAC,IEEE Transactions on Circuits and Systems Part II, vol. 53, no. 9, pp. 848–852, 2006.
[362] Chan, K. L. and Galton, I., “A 14 b 100 MS/s DAC with fully segmented dynamic element matching,” in International Solid-State Circuits Conference, 2006, pp. 582–583.
[363] Chan, K. L., Zhu, J., and Galton, I., “A 150 MS/s 14-bit segmented DEM DAC with greater than 83 dB of SFDR across the Nyquist band,” in VLSI Circuits Conference, 2007, pp. 200–201.
[364] Chan, K. L., Rakulijc, N., and Galton, I., “Segmented dynamic element matching for highresolution digital-to-analog conversion,IEEE Transactions on Circuits and Systems Part I, vol. 55, no. 11, pp. 3383–3392, 2008.
[365] Lin, T. and Samueli, H., “A 200-MHz CMOS x sin(x) digital filter for compensating D/A converter frequency response distortion,IEEE International Journal of Solid StateCircuits, vol. 26, pp. 1278–1285, 1991.
[366] Gupta, A. K., Venkataraman, J., and Collins, O. M., “Measurement and reduction of ISI in high-dynamic-range 1-bit signal generation,IEEE Transactions on Circuits and Systems Part I, vol. 55, no. 11, pp. 3593–3606, 2008.
[367] Li, Y. and Schafferer, B., “Mixer/DAC chip and method,” International Patent WO 2008/112 348 A1, 2008.
[368] Li, Y. and Schafferer, B., “Mixer/DAC chip and method,” US Patent 7 796 971, 2010.
[369] Zeijl, P. T. M. and Collados, M., “On the attenuation of DAC aliases through multiphase clocking,IEEE Transactions on Circuits and Systems Part II, vol. 56, no. 3, pp. 190–194, 2009.
[370] Zhou, Y. and Yuan, J., “A 10-bit wide-band CMOS direct digital RF amplitude modulator,IEEE International Journal of Solid State Circuits, vol. 38, no. 7, pp. 1182–1188, 2003.
[371] Deveugele, J., Palmers, P., and Steyaert, M. S. J., “Parallel-path digital-to-analog converters for Nyquist signal generation,IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1073–1082, 2004.
[372] Franca, J., Petraglia, A., and Mitra, S. K., “Multirate analog-digital systems for signal processing and conversion,Proceedings of the IEEE, vol. 85, no. 2, pp. 242–262, 1997.
[373] ,Analog Devices Staff, “A technical tutorial on digital signal synthesis,” Analog Devices, Application Note, 1999.
[374] Lee, K., Meng, Q., Sugimoto, T.et al., “A 0.8 V, 2.6 mW, 88 dB dual-channel audio deltasigma D/A converter with headphone driver,IEEE International Journal of Solid State Circuits, vol. 44, no. 3, pp. 916–927, 2009.
[375] Colonna, V., Annovazzi, M., Boarin, G.et al., “A 0.22-mm2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNRout,IEEE International Journal of Solid State Circuits, vol. 40, no. 7, pp. 1491–1498, 2005.
[376] Nguyen, K. and Schreier, R., “System and method for tri-level logic data shuffling for oversampling data conversion,” US Patent 7 079 063, 2006.
[377] Bandyopadhyay, A., Determan, M., Kim, S., and Nguyen, K., “A 120 dB SNR, 100 dB THD+N, 21.5 mW/channel multibit continuous time Δσ DAC,” in International Solid- State Circuits Conference, 2011, pp. 482–483.
[378] Hezar, R., Risbo, L., Kiper, H.et al., “A 110 dB SNR and 0.5mWcurrent-steering audio DAC implemented in 45 nm CMOS,” in International Solid-State Circuits Conference, 2010, pp. 304–307.
[379] Risbo, L., Hezar, R., Kelleci, B., Kiper, H., and Fares, M., “A 108 dB DR, 120 dB THD and 0.5Vrms output audio DAC with inter-symbol-interference shaping algorithm in 45 nm,” in International Solid-State Circuits Conference, 2011, pp. 484–485.
[380] Vankka, J., Digital Synthesizers and Transmitters for Software Radio, 1st edn. Springer- Verlag, Berlin, Germany, July 2005.
[381] Nicholas, H. T. III and Samueli, H., “A 150-MHz direct digital frequency synthesizer in 1.25-μm CMOS with -90-dBc spurious performance,IEEE International Journal of Solid State Circuits, vol. 26, no. 12, pp. 1959–1969, 1991.
[382] Caro, D., Petra, N., and Strollo, A. G. M., “A 380 MHz direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25 μmCMOS,IEEE International Journal of Solid State Circuits, vol. 42, no. 1, pp. 151–160, 2007.
[383] Kang, C. Y. and Swartzlander, E. E. Jr., “Digit-pipelined direct digital frequency synthesis based on differential CORDIC,IEEE Transactions on Circuits and Systems Part I, vol. 53, no. 5, pp. 1035–1044, 2006.
[384] Ashrafi, A., Adhami, R., and Milenković, A., “A direct digital frequency synthesizer based on the quasi-linear interpolation method,IEEE Transactions on Circuits and Systems Part I, vol. 57, no. 4, pp. 863–872, 2010.
[385] Caro, D. and Strollo, A. G. M., “High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation,IEEE International Journal of Solid State Circuits, vol. 40, no. 11, pp. 2220–2227, 2005.
[386] Dai, F. F., Ni, W., Yin, S., and Jaeger, R. C., “A direct digital frequency synthesizer with fourthorder phase domain Δσ noise shaper and 12-bit current-steering DAC,IEEE International Journal of Solid State Circuits, vol. 41, no. 4, pp. 839–850, 2006.
[387] McEwan, A. and Collins, S., “Direct digital-frequency synthesis by analog interpolation,IEEE Transactions on Circuits and Systems Part II, vol. 53, no. 11, pp. 1294–1298, 2006.
[388] Thuries, S., Tournier, E., Cathelin, A., Godet, S., and Graffeuil, ., “A 6-GHz low-power BiCMOS SiGe:C 0.25 μm direct digital synthesizer,IEEE Microwave and Wireless Components Letters, vol. 18, no. 1, pp. 46–48, 2008.
[389] Mortezapour, S. and Lee, E. K. F., “Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,IEEE International Journal of Solid State Circuits, vol. 34, no. 10, pp. 1350–1359, 1999.
[390] Jiang, J. and Lee, E. K. F., “A low-power segmented nonlinear DAC-based direct digital frequency synthesizer,IEEE International Journal of Solid State Circuits, vol. 37, no. 10, pp. 1326–1330, 2002.
[391] Turner, S. E. and Kotecki, D. E., “Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in InP DHBT technology,IEEE International Journal of Solid State Circuits, vol. 41, no. 10, pp. 2284–2290, 2006.
[392] Zhou, Z. and Rue, G. S. L., “A 12-bit nonlinear DAC for direct digital frequency synthesis,IEEE Transactions on Circuits and Systems Part I, vol. 55, no. 9, pp. 2459–2468, 2008.
[393] Geng, X., Dai, F. F., Irwin, J.D., and Jaeger, R. C., “An 11-bit 8.6 GHz direct digital synthesizer MMIC with 10-bit segmented sine-weighted DAC,IEEE International Journal of Solid State Circuits, vol. 45, no. 2, pp. 300–313, 2010.
[394] Yeoh, H. C., Jung, J.-H., Jung, Y.-H., and Baek, K.-H., “A 1.3-GHz 350-mW hybrid direct digital frequency synthesizer in 90-nm CMOS,IEEE International Journal of Solid State Circuits, vol. 45, no. 9, pp. 1845–1855, 2010.
[395] Savoj, J., Abbasfar, A., Amirkhany, A., Jeeradit, M., and Garlepp, B. W., “A 12-GS/s phasecalibrated CMOS digital-to-analog converter for backplane communications,IEEE International Journal of Solid State Circuits, vol. 43, no. 5, pp. 1207–1216, 2008.
[396] Luschas, S., Schreier, R., and Lee, H.-S., “Radio frequency digital-to-analog converter,IEEE International Journal of Solid State Circuits, vol. 39, no. 9, pp. 1462–1467, 2004.
[397] Luschas, S. and Lee, H.-S., “High-speed Δσ modulators with reduced timing jitter sensitivity,IEEE Transactions on Circuits and Systems Part II, vol. 49, no. 11, pp. 712–720, 2002.
[398] Eloranta, P. and Seppinen, P., “Direct-digital RF modulator IC in 0.13 μm CMOS for wideband multi-radio applications,” in International Solid-State Circuits Conference, 2005, pp. 532–533.
[399] Jerng, A. and Sodini, C. G., “A wideband Δσ digital-RF modulator for high data rate transmitters,IEEE International Journal of Solid State Circuits, vol. 42, no. 8, pp. 1710– 1722, 2007.
[400] Razavi, B., RF Microelectronics. Prentice Hall, New York, NY, 1998.
[401] Eloranta, P., Seppinen, P., Kallioinen, S., Saarela, T., and Pärssinen, A., “A multimode transmitter in 0.13 μm CMOS using direct-digital RF modulator,IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2774–2784, 2007.
[402] Zimmermann, N., Negra, R., and Heinen, S., “Design of an RF-DAC in 65 nm CMOS for multistandard, multimode transmitters,” in IEEE International Symposium on Radio- Frequency Integration Technology, 2009, pp. 343–346.
[403] Taleie, S. M., Copani, T., Bakkaloglu, B., and Kiaei, S., “A linear Δ–σ digital IF to RF DAC transmitter with embedded mixer,IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1059–1068, 2008.
[404] Park, M., Perrott, M. H., and Staszewski, R. B., “A time-domain resolution improvement of an RF-DAC,IEEE Transactions on Circuits and Systems Part II, vol. 57, no. 7, pp. 517–521, 2010.
[405] Jonsson, B. E., “A survey of A/D-converter performance evolution,” in IEEE International Conference on Electronics, Circuits, and Systems, 2010, pp. 768–771.
[406] Sundström, T., Murmann, B., and Svensson, C., “Power dissipation bounds for high-speed Nyquist analog-to-digital converters,IEEE Transactions on Circuits and Systems Part I, vol. 56, no. 3, pp. 509–518, 2009.
[407] Wu, J.-Y., Subramoniam, R., Zhang, Z.et al., “Multi-bit sigma delta ADC with reduced feedback levels, extended dynamic range and increased tolerance for analog imperfections,” in Custom Integrated Circuits Conference, 2007, pp. 77–80.
[408] Farahani, B. J., Krishna, S. G., Venkatesan, S.et al., “Wide-temperature high-resolution integrated data acquisition for spectroscopy in space,” in IEEE Aerospace Conference, 2011.
[409] Sheikholeslami, A., Payne, R., and Lin, J., “ISSCC 2009 evening session on 'will ADCs overtake binary frontends in backplane signaling?',” in International Solid-State Circuits Conference, IEEE, 2 2009.
[410] Chen, E.-H. and Yang, C.-K. K., “ADC-based serial I/O receivers,IEEE Transactions on Circuits and Systems Part I, vol. 57, no. 9, pp. 2248–2258, 2010.
[411] Wegener, A., “Compression of medical sensor data [exploratory DSP],IEEE Signal Processing Magazine, vol. 27, no. 4, pp. 125–130, 2010.
[412] Löwenborg, P., Johansson, H., and Wanhammar, L., “Two-channel digital and hybrid analog/ digital multirate filter banks with very low-complexity analysis or synthesis filters,IEEE Transactions on Circuits and Systems Part II, vol. 50, no. 7, pp. 355–367, 2003.
[413] Johansson, H. and Löwenborg, P., “A least-squares filter design technique for the compensation of frequency response mismatch errors in time-interleaved A/D converters,IEEE Transactions on Circuits and Systems -Part II, vol. 55, no. 11, pp. 1154–1158, 2008.
[414] Xiong, W., Zschieschang, U., Klauk, H., and Murmann, B., “A3V6b successive-approximation ADC using complementary organic thin-film transistors on glass,” in International Solid- State Circuits Conference, 2010, pp. 134–135.
[415] Marien, H., Steyaert, M., Aerle, N., and Heremans, P., “An analog organic first-order ct Δσ ADC on a flexible plastic substrate with 26.5 dB precision,” in International Solid-State Circuits Conference, 2010, pp. 136–137.
[416] Zaki, T., Ante, F., Zschieschang, U., Butschke, J., Letzkus, F., Richter, H., Klauk, H., and Burghartz, J. N., “A 3.3 V 6b 100 kS/s current-steering D/A converter using organic thin-film transistors on glass,” in International Solid-State Circuits Conference, 2011, pp. 324–325.

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