As briefly mentioned in Section 2.4, a variety of DAC architectures have been developed and are being utilized, depending on signal-bandwidth and dynamic-range needs. These include capacitive DACs, resistive DACs, and current-steering DACs among others. The former two categories are routinely used either for stand-alone converters for precision applications or as internal sub-blocks for all types of ADCs. However, the current-steering architecture is certainly the one which has recently received the most attention, across a large resolution range, due to its inherent high speed and its ability to directly drive low-impedance loads (notably resistors). It is for this reason that this chapter will cover only current-steering DACs.

The chapter is organized as follows. First the basics of this architecture are briefly summarized for convenience. That includes a discussion of segmentation. Static linearity is then the topic of Section 4.2, where the causes of static linearity errors and techniques by which to minimize them are discussed. That is followed by a discussion on “intrinsic-matching DACs” where static linearity is guaranteed by design. Next, traditional as well as advanced calibration techniques are covered as an alternate approach to address mismatch errors, freeing up the designer to focus on other dimensions such as silicon area or dynamic performance.

Various sources of dynamic linearity errors are discussed in Section 4.3. Their detrimental effects leading to high-frequency distortion are described. This is followed by an account of a variety of circuits and techniques to mitigate these issues in Section 4.3.3.