A feedback with carry shift register is a feedback shift register with a small amount of auxiliary memory. In its simplest form, the cells of the register consist of bits (0 or 1) while the memory contains a nonnegative integer. The contents (0 or 1) of the tapped cells of the shift register are added as integers to the current contents of the memory to form a sum σ. The parity bit, σ (mod 2) of σ is fed back into the first cell, and the higher order bits, └σ/2┘ are retained for the new value of the memory. See Figure 4.1. There are many parallels between LFSR sequences and FCSR sequences, some of which we list in Table 4.1.

The output sequences generated by an FCSR are examples of multiply with carry sequences. They enjoy many of the useful statistical properties of linearly recurrent sequences. As with linearly recurrent sequences, several algebraic structures are available for the analysis of multiply with carry sequences, including ordinary integer arithmetic, N-adic numbers, and an analog of the trace function. Multiply with carry sequences have been applied in such areas as pseudo-random number generation, cryptanalysis, stream cipher design, and arithmetic codes.

FCSRs were first described in the early 1990s [67, 115, 119]. These devices were suggested as a method for high speed hardware generation of binary sequences with enormous periods, as might be used in a stream cipher or digital communication system.