Book contents
- Frontmatter
- Contents
- Preface
- Introduction
- Acknowledgments
- Contributors
- Acronyms and Abbreviations
- Boolean Models and Methods in Mathematics, Computer Science, and Engineering
- Part I Algebraic Structures
- Part II Logic
- Part III Learning Theory and Cryptography
- Part IV Graph Representations and Efficient Computation Models
- Part IV Applications in Engineering
- 15 Hardware Equivalence and Property Verification
- 16 Synthesis of Multilevel Boolean Networks
15 - Hardware Equivalence and Property Verification
from Part IV - Applications in Engineering
Published online by Cambridge University Press: 05 June 2013
- Frontmatter
- Contents
- Preface
- Introduction
- Acknowledgments
- Contributors
- Acronyms and Abbreviations
- Boolean Models and Methods in Mathematics, Computer Science, and Engineering
- Part I Algebraic Structures
- Part II Logic
- Part III Learning Theory and Cryptography
- Part IV Graph Representations and Efficient Computation Models
- Part IV Applications in Engineering
- 15 Hardware Equivalence and Property Verification
- 16 Synthesis of Multilevel Boolean Networks
Summary
Introduction to Formal Verification
The Problem of Verification
Synthesis and verification are two basic steps in designing a digital electronic system, which may involve both hardware and software components. Synthesis aims to produce an implementation that satisfies the specification while minimizing some cost objectives, such as circuit area, code size, timing, and power consumption. Verification deals with the certification that the synthesized component is correct.
In system design, hardware synthesis and verification are more developed than the software counterparts and will be our focus. The reason for this asymmetric development is threefold. First, hardware design automation is better driven by industrial needs; after all, hardware costs aremore tangible. Second, the correctness and time-to-market criteria of hardware design are in general more stringent. As a result, hardware design requires rigorous design methodology and high automation. Third, hardware synthesis and verification admit simpler formulation and are better studied.
There are various types of hardware verification, according to design stages, methodologies, and objectives. By design stages, verification can be deployed in high-level design from specification, called design verification; during synthesis transformation, called implementation verification; or after circuit manufacturing, called manufacture verification.
Manufacture verification is also known as testing. There is a whole research and engineering community devoted to it. In hardware testing, we would like to know if some defects appear in a manufactured circuit by testing the conformance between it and its intended design.
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- Publisher: Cambridge University PressPrint publication year: 2010