Introduction to Formal Verification

The Problem of Verification

Synthesis and verification are two basic steps in designing a digital electronic system, which may involve both hardware and software components. Synthesis aims to produce an implementation that satisfies the specification while minimizing some cost objectives, such as circuit area, code size, timing, and power consumption. Verification deals with the certification that the synthesized component is correct.

In system design, hardware synthesis and verification are more developed than the software counterparts and will be our focus. The reason for this asymmetric development is threefold. First, hardware design automation is better driven by industrial needs; after all, hardware costs aremore tangible. Second, the correctness and time-to-market criteria of hardware design are in general more stringent. As a result, hardware design requires rigorous design methodology and high automation. Third, hardware synthesis and verification admit simpler formulation and are better studied.

There are various types of hardware verification, according to design stages, methodologies, and objectives. By design stages, verification can be deployed in high-level design from specification, called design verification; during synthesis transformation, called implementation verification; or after circuit manufacturing, called manufacture verification.

Manufacture verification is also known as testing. There is a whole research and engineering community devoted to it. In hardware testing, we would like to know if some defects appear in a manufactured circuit by testing the conformance between it and its intended design.