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3 - CMOS technology, components, and layout techniques

Published online by Cambridge University Press:  17 December 2010

Márcio Cherem Schneider  and
Carlos Galup-Montoro
Márcio Cherem Schneider
Affiliation:
Universidade Federal de Santa Catarina, Brazil
Carlos Galup-Montoro
Affiliation:
Universidade Federal de Santa Catarina, Brazil
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Summary

This chapter begins with a rapid overview of CMOS technology for circuit designers, including the description of a simplified deep-submicron CMOS structure and its process flow as well as the main parameters of some representative processes. The devices available in CMOS processes, including resistors, capacitors, inductors, and bipolar transistors, are then reviewed. The main electrical parameters of the passive devices are presented. Some design issues related to the use of sub-wavelength optical lithography are addressed in the introduction to the layout sections. Finally, layout topics, including design rules and layout for manufacturability, for matching, and for transistor associations, are presented.

An overview of CMOS technology

MOS integrated circuits (ICs) have been manufactured for volume delivery ever since 1970. Taking advantage of the scalability of the MOS transistors, micron technologies were developed during the 1980s and deep-submicron technologies appeared in the 1990s. In this chapter we will briefly review some deep-submicron processes that are currently (2009) employed for analog design.

Basic process steps in monolithic IC fabrication

Monolithic ICs are fabricated on high-quality monocrystalline silicon substrates called wafers, with diameters as large as 300 mm and thicknesses up to 1250 μm. The fabrication process enables the achievement of appropriate geometries in the semiconductor and in the insulating and conducting layers deposited on the semiconductor substrate. The fabrication process consists of a series of elementary steps that allows the patterning of the semiconductor substrate and the modification of its electrical properties by selective doping as well as the deposition, removal, and patterning of conducting and insulating layers.

Type
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CMOS Analog Design Using All-Region MOSFET Modeling , pp. 88 - 133
Publisher: Cambridge University Press
Print publication year: 2010

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