CMOS technology, components, and layout techniques

Márcio Cherem Schneider; Carlos Galup-Montoro

doi:10.1017/CBO9780511803840.004

3 - CMOS technology, components, and layout techniques

Published online by Cambridge University Press: 17 December 2010

Márcio Cherem Schneider and

Carlos Galup-Montoro

Show author details

Márcio Cherem Schneider: Affiliation:
Universidade Federal de Santa Catarina, Brazil
Carlos Galup-Montoro: Affiliation:
Universidade Federal de Santa Catarina, Brazil

Book contents

Get access

Summary

This chapter begins with a rapid overview of CMOS technology for circuit designers, including the description of a simplified deep-submicron CMOS structure and its process flow as well as the main parameters of some representative processes. The devices available in CMOS processes, including resistors, capacitors, inductors, and bipolar transistors, are then reviewed. The main electrical parameters of the passive devices are presented. Some design issues related to the use of sub-wavelength optical lithography are addressed in the introduction to the layout sections. Finally, layout topics, including design rules and layout for manufacturability, for matching, and for transistor associations, are presented.

An overview of CMOS technology

MOS integrated circuits (ICs) have been manufactured for volume delivery ever since 1970. Taking advantage of the scalability of the MOS transistors, micron technologies were developed during the 1980s and deep-submicron technologies appeared in the 1990s. In this chapter we will briefly review some deep-submicron processes that are currently (2009) employed for analog design.

Basic process steps in monolithic IC fabrication

Monolithic ICs are fabricated on high-quality monocrystalline silicon substrates called wafers, with diameters as large as 300 mm and thicknesses up to 1250 μm. The fabrication process enables the achievement of appropriate geometries in the semiconductor and in the insulating and conducting layers deposited on the semiconductor substrate. The fabrication process consists of a series of elementary steps that allows the patterning of the semiconductor substrate and the modification of its electrical properties by selective doping as well as the deposition, removal, and patterning of conducting and insulating layers.

Type: Chapter
Information: CMOS Analog Design Using All-Region MOSFET Modeling , pp. 88 - 133

DOI: https://doi.org/10.1017/CBO9780511803840.004 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2010

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Book purchase

Temporarily unavailable

References

Taur, Y. and Ning, T. H., Fundamentals of Modern VLSI Devices, Cambridge: Cambridge University Press, 1998.Google Scholar

Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, 4th edn., New York: John Wiley & Sons, 2001.Google Scholar

Jaeger, R. C., Introduction to Microelectronic Fabrication, 2nd edn., Upper Saddle River, NJ: Prentice Hall, 2002.Google Scholar

Wong, B. P., Mittal, A., Cao, Y., and Starr, G., Nano-CMOS Circuit and Physical Design, Hoboken, NJ: Wiley-Interscience, 2005.Google Scholar

Baker, R. Jacob, CMOS Circuit Design, Layout, and Simulation, 2nd edn., Hoboken, NJ: IEEE Press and Wiley-Interscience, 2005.Google Scholar

Taur, Y., Chang, W. H., and Dennard, R. H., “Characterization and modeling of a latchup free 1-μm CMOS technology,” IEDM Technical Digest, 1984, pp. 398–401.Google Scholar

Yang, S., Ahmed, S., Arcot, B.et al., “A high performance 180 nm generation logic technology,” IEDM Technical Digest, 1998, pp. 197–200.Google Scholar

Chang, W.-H., Davari, B., Wordeman, M. R.et al., “A high-performance 0.25-μm CMOS technology: I – Design and characterization,” IEEE Transactions on Electron Devices, vol. 39, no. 4, pp. 959–966, Apr. 1992.CrossRef Google Scholar

Davari, B., Chang, W.-H., Petrillo, K. E.et al., “A high-performance 0.25-μm CMOS technology: II – Technology,” IEEE Transactions on Electron Devices, vol. 39, no. 4, pp. 967–975, Apr. 1992.CrossRef Google Scholar

Bohr, M., Ahmed, S. U., Brigham, L.et al., “A high performance 0.35 μm logic technology for 3.3 and 2.5 V operation,” IEDM Technical Digest, 1994, pp. 273–276.Google Scholar

Holloway, T. C., Dixit, G. A., Grider, D. T.et al., “0.18 μm CMOS technology for high-performance, low-power, and RF applications,” Symposium on VLSI Technical Digest, 1997, pp. 13–14.CrossRef Google Scholar

Ikeda, S., Yoshida, Y., Shoji, K.et al., “A highly manufacturable 0.18 μm generation LOGIC technology,” IEDM Technical Digest, 1999, pp. 675–678.Google Scholar

Wann, C., Harrington, J., Mih, R.et al., “CMOS with active well bias for low-power and RF/analog applications,” Symposium on VLSI Technical Digest, 2000, pp. 158–159.Google Scholar

Chatterjee, A., Mosher, D., Sridhar, S.et al., “Analog integration in a 0.35 μm Cu metal pitch, 0.1 μm gate length, low-power digital CMOS technology,” IEDM Technical Digest, 2001, pp. 211–214.Google Scholar

Kirchgessner, J., Bigelow, S., Chai, F. K.et al. “A 0.18 μm SiGe : C RFBiCMOS technology for wireless and gigabit optical communication applications,” IEEE BCTM Technical Digest, 2001, pp. 151–154.Google Scholar

Yanagiya, N., Matsuda, S., Inaba, S.et al., “65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications,” IEDM Technical Digest, 2002, pp. 57–60.Google Scholar

Thompson, S., Anand, N., Armstrong, M.et al., “A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell,” IEDM Technical Digest, 2002, pp. 61–64.Google Scholar

Wu, C. C., Leung, Y. K., Chang, C. S.et al., “A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” IEDM Technical Digest, 2002, pp. 65–68.Google Scholar

Kim, Y. W., Oh, C. B., Ko, Y. G.et al., “50 nm gate length logic technology with 9-layer Cu interconnects for 90 nm node SoC applications,” IEDM Technical Digest, 2002, pp. 69–72.Google Scholar

Kuhn, K., Agostinelli, M., Ahmed, S.et al., “A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R–L–C RF elements and 1 μm2 6-T SRAM cell,” IEDM Technical Digest, 2002, pp. 73–76.Google Scholar

MOSIS Integrated Circuits Fabrication Service, www.mosis.org.

Shackelford, J. F., Introduction to Materials Science for Engineers, 4th edn., Upper Saddle River, NJ: Prentice Hall, 1996.Google Scholar

Hamilton, D. J. and Howard, W. G., Basic Integrated Circuit Engineering, Tokyo: McGraw-Hill Kogakusha, 1975.Google Scholar

Hastings, A., The Art of Analog Layout, Upper Saddle River, NJ: Prentice Hall, 2001.Google Scholar

Allstot, D. J. and Black, W. C., “Technological design considerations for monolithic MOS switched-capacitor filtering systems,” Proceedings of the IEEE, vol. 71, pp. 967–986, Aug. 1983.CrossRef Google Scholar

Lane, W. A. and Wrixon, G. T., “The design of thin-film polysilicon resistors for analog IC applications,” IEEE Transactions on Electron Devices, vol. 36, no. 4, pp. 738–744, Apr. 1989.CrossRef Google Scholar

Liu, W.-C., Thei, K.-B., Chuang, H.-M.et al., “Characterization of polysilicon resistors in sub-0.25 μm CMOS ULSI applications,” IEEE Electron Device Letters, vol. 22, no. 7, pp. 318–320, July 2001.Google Scholar

Chuang, H.-M., Thei, K.-B., Tsai, S.-F., and Liu, W.-C., “Temperature-dependent characteristics of polysilicon and diffused resistors,” IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1413–1415, May 2003.CrossRef Google Scholar

Grove, A. S., Physics and Technology of Semiconductor Devices, New York: John Wiley & Sons, 1967.Google Scholar

Booth, R. V. H. and McAndrew, C. C., “A 3-terminal model for diffused and ion-implanted resistors,” IEEE Transactions on Electron Devices, vol. 44, no. 5, pp. 809–814, May 1997.CrossRef Google Scholar

Niknejad, A. M. and Boser, B. E., EECS 240 Analog Integrated Circuits, http://rfic.eecs.berkeley.edu/~niknejad/ee240sp06.

Sze, S. M., Physics of Semiconductor Devices, New York: John Wiley & Sons, 1969.Google Scholar

Behr, A. T., Schneider, M. C., Filho, S. Noceti, and Montoro, C. Galup, “Harmonic distortion caused by capacitors implemented with MOSFET gates,” IEEE Journal of Solid-State Circuits, vol. 27, no. 10, pp. 1470–1475, Oct. 1992.CrossRef Google Scholar

McCreary, J. L., “Matching properties, and voltage and temperature dependence of MOS capacitors,” IEEE Journal of Solid-State Circuits, vol. 16, no. 6, pp. 608–616, Dec. 1981.CrossRef Google Scholar

Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn., New York: Cambridge University Press, 2004.Google Scholar

Aparicio, R. and Hajimiri, A., “Capacity limits and matching properties of lateral flux integrated capacitors,” CICC Technical Digest, 2001, pp. 365–368.Google Scholar

Slater, D. B. and Paulos, J. J., “Low-voltage coefficient capacitors for VLSI processes,” IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 165–173, Feb. 1989.CrossRef Google Scholar

Lakshmikumar, K. R., Hadaway, R. H., and Copeland, M. A., “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 1057–1066, Dec. 1986.CrossRef Google Scholar

Pu, L.-J. and Tsividis, Y., “Transistor-only frequency-selective circuits,” Proceedings of IEEE ISCAS, 1988, pp. 2851–2854.Google Scholar

Porret, A.-S., Design of a Low-Power and Low-Voltage UHF Transceiver Integrated in a CMOS Process, PhD Thesis, EPFL, Lausanne, 2002.

Mohan, S. S., Hershenson, M. del Mar, Boyd, S. P., and Lee, T. H., “Simple accurate expressions for planar spiral inductances,” IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1419–1424, Oct. 1999.CrossRef Google Scholar

Park, M., Lee, S., Kim, C. S., Yu, H. K., and Nam, K. S., “The detailed analysis of high Q CMOS-compatible microwave spiral inductors in silicon technology,” IEEE Transactions on Electron Devices, vol. 45, no. 9, pp. 1953–1959, Sep. 1998.CrossRef Google Scholar

Ramo, S., Whinnery, J. R., and Duzer, T., Fields and Waves in Communication Electronics, New York: John Wiley & Sons, 1965.Google Scholar

MacSweeney, D., McCarthy, K. G., Mathewson, A., and Mason, B., “A SPICE compatible subcircuit model for lateral bipolar transistors in a CMOS process,” IEEE Transactions on Electron Devices, vol. 45, no. 9, pp. 1978–1984, Sep. 1998.CrossRef Google Scholar

Vittoz, E. A., “MOS transistors operated in the lateral bipolar model and their application in CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 18, no. 3, pp. 273–279, June 1983.CrossRef Google Scholar

Nam, I., Kim, Y. J., and Lee, K., “Low 1/f noise and DC offset RF mixer for direct conversion receiver using parasitic vertical NPN bipolar transistor in deep N-well CMOS technology,” Symposium on VLSI Circuits Digest, 2003, pp. 223–226.Google Scholar

Ker, M.-D., Jiang, H.-C., Peng, J.-J., and Shieh, T.-L., “Automatic methodology for placing the guard ring into chip layout to prevent latchup in CMOS IC's,” Proceedings of IEEE ICECS, 2001, pp. 113–116.Google Scholar

Rieger, M. L., Mayhew, J. P., and Panchapakesan, S., “Layout design methodologies for sub-wavelength manufacturing,” Proceedings of DAC, 2001, pp. 85–88.Google Scholar

Liebmann, L. W., “Layout impact of resolution enhancement techniques: impediment or opportunity?,” Proceedings of the International Symposium on Physical Design, 2003, pp. 110–117.Google Scholar

Kawa, J., Chiang, C., and Camposano, R., “EDA challenges in nano-scale technology,” CICC Technical Digest, 2006, pp. 845–851.Google Scholar

Kawa, J. and Chiang, C., “DFM issues for 65 nm and beyond,” Proceedings of GLSVLSI, 2007, pp. 318–322.Google Scholar

Vittoz, E., “Layout techniques for analog circuits,” Intensive Summer Course on CMOS VLSI Design, EPFL, Lausanne, July 1989.Google Scholar

Schmerbeck, T., “Analog and mixed signal circuit layout techniques and floorplanning,” Advanced Engineering Course on Practical Aspects in Analog and mixed ICs, EPFL, Lausanne, July 1994.Google Scholar

Mead, C., Analog VLSI and Neural Systems, Reading, MA: Addison-Wesley, 1989.Google Scholar

Liu, S.-C., Kramer, J., Indiveri, G., Delbrück, T., and Douglas, R., Analog VLSI: Circuits and Principles, Cambridge, MA: MIT Press, 2002.Google Scholar

Maloberti, F., Analog Design for CMOS VLSI Systems, Boston, MA: Kluwer Academic Publishers, 2001.Google Scholar

Gatti, U. and Maloberti, F., “Analog and mixed analog-digital layout,” in Analog VLSI – Signal and Information Processing, ed. Ismail, M. and Fiez, T., New York: McGraw-Hill, 1994, pp. 699–726.Google Scholar

Tsividis, Y., Mixed Analog-Digital VLSI Devices and Technology, New York: McGraw-Hill, 1996.Google Scholar

Razavi, B., Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.Google Scholar

Vittoz, E., “The design of high-performance analog circuits on digital CMOS chips,” IEEE Journal of Solid-State Circuits, vol. 20, no. 3, pp. 657–665, June 1985.CrossRef Google Scholar

Pelgrom, M. J. M., Duinmaijer, A. C. J., and Welbers, A., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433–1440, Oct. 1989.CrossRef Google Scholar

Galup-Montoro, C., Schneider, M. C., Klimach, H., and Arnaud, A., “A compact model of MOSFET mismatch for circuit design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1649–1657, Aug. 2005.CrossRef Google Scholar

Galup-Montoro, C., Schneider, M. Cherem, and Loss, I. J. B., “Series-parallel association of FET's for high gain and high frequency applications,” IEEE Journal of Solid-State Circuits, vol. 29, no. 98, pp. 1094–1101, Sep. 1994.CrossRef Google Scholar

Arnaud, A., Fiorelli, R., and Galup-Montoro, C., “Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors”, IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2009–2018, Sep. 2006.CrossRef Google Scholar

Schmerbeck, T., “Mechanisms and effects of noise coupling in analog and mixed signal ICs,” Advanced Engineering Course on Practical Aspects in Analog and mixed ICs, EPFL, Lausanne, July 1994.Google Scholar

Galup-Montoro, C. and Schneider, M. C., MOSFET Modeling for Circuit Analysis and Design, Singapore: World Scientific, 2007.CrossRef Google Scholar