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Chapter 3 - Functional Verification

Hubert Kaeslin
Affiliation:
ETH Zürich
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Summary

The ultimate goal of design verification is to avoid the manufacturing and deployment of flawed designs. Large sums of money are wasted and precious time to market is lost when a microchip does not perform as expected. Any design is, therefore, subject to detailed verification long before manufacturing begins and to thorough testing following fabrication. One can distinguish three motivations (after the late A. Richard Newton):

  1. During specification: “Is what I am asking for what is really needed?”

  2. During design: “Have I indeed designed what I have asked for?”

  3. During testing: “Can I tell intact circuits from malfunctioning ones?”

In any of these cases, one can focus on different circuit properties.

Functionality describes what responses a system produces at the output when presented with given stimuli at the input. In the context of digital ICs, we tend to think of logic networks and of package pins but the concept of input-to-output mapping applies to information processing systems in general. Functionality gets expressed in terms of mathematical concepts such as algorithms, equations, impulse responses, tolerance bands for numerical inaccuracies, finite state machines (FSM), and the like, but often also informally.

Parametric properties, in contrast, relate to physical quantities measured in units such as Mbit/s, ns, V, μA, mW, pF, etc. that serve to express electrical and timing-related characteristics of an electronic circuit.

Observation 3.1.Experience has shown that a design's functionality and its parametric properties are best checked separately since goals, methods, and tools are quite different.

Type
Chapter
Information
Digital Integrated Circuit Design
From VLSI Architectures to CMOS Fabrication
, pp. 136 - 174
Publisher: Cambridge University Press
Print publication year: 2008

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  • Functional Verification
  • Hubert Kaeslin, ETH Zürich
  • Book: Digital Integrated Circuit Design
  • Online publication: 05 November 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511805172.004
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  • Functional Verification
  • Hubert Kaeslin, ETH Zürich
  • Book: Digital Integrated Circuit Design
  • Online publication: 05 November 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511805172.004
Available formats
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Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

  • Functional Verification
  • Hubert Kaeslin, ETH Zürich
  • Book: Digital Integrated Circuit Design
  • Online publication: 05 November 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511805172.004
Available formats
×