Scaling on-chip Cu wiring dimensions has degraded electromigration (EM) reliability with the same metallization and rapidly increased Cu resistivity. The size effects in EM and resistivity were caused by increased contributions from EM-induced mass flow and electron scattering with interfaces and grain boundaries, respectively. The EM Cu interconnect lifetime had further degraded by the decrease in the void volume required to cause EM failure. The Cu interconnect resistance was further increased by increasing the volume fraction of barrier/liner in metal wires that were required to produce chips with good reliability. In this chapter, we review the Cu microstructure and resistivity for various CMOS technological nodes, the basic physics of the EM phenomenon addressing EM mass transport, lifetime scaling rule, and damage formation in Cu damascene line structures. This is followed with discussions on Blech short length and EM scaling rule. Several techniques developed for improving EM reliability using upper-level dummy vias, impurities, Cu surface treatments, alternated liners, and surface metal coating are discussed together with the effects of Cu microstructure, atomic layer deposition MnOx liner, and Cu/carbon nanotube composite line on EM.Finally, the EM lifetimes, failure mechanisms and activation energies through various technological nodes are presented.