Amorphous thin films of composition TixSi1-xO2 have been grown by low pressure chemical vapor deposition on silicon (100) substrates using Si(O-Et)4 and either Ti(O-iPr)4 or anhydrous Ti(NO3)4 as the sources of SiO2 and TiO2, respectively. The substrate temperature was varied between 300 and 535°C, and the precursor flow rates ranged from 5 to 100 sccm. Under these conditions growth rates ranging from 0.6 to 90.0 nm/min were observed. As-deposited films were amorphous to X-rays and SEM micrographs showed smooth, featureless film surfaces. Cross-sectional TEM showed no compositional inhomogeneity. RBS revealed that x (from the formula TixSi1-xO2) was dependent upon the choice of TiO2 precursor. For films grown using TTIP-TEOS x could be varied by systematic variation of the deposition conditions. For the case of TN-TEOS x remained close to 0.5 under all conditions studied. One explanation is the existence of a specific chemical reaction between TN and TEOS prior to film deposition. TEOS was mixed with a CCl4 solution of TN at room temperature to produce an amorphous white powder (Ti/Si = 1.09) and 1HNMR of the CCl4 solution indicated resonances attributable to ethyl nitrate.

CoSi2 has emerged as the silicide of choice for 0.18μm CMOS technologies and below. Robustness and scaling-performance of an integrated CoSi2-module, however, is shown to critically depend upon careful optimization of each individual process-step. The impact of surface-preparation, capping layer, initial Co-thickness and thermal processing will be discussed. The scalability of an optimized process meeting all major requirements for application to ULSI devices is demonstrated for gate-length down to 60nm.

A low-complexity and low-cost double-metal BiCMOS process is proposed with only 13 mask steps. By decoupling the source-drain thermal budget from gate-stack formation, metal gates are realizable.

The effect of a thin Ta layer at the Ti/Si interface on the kinetic of the C49-C54 transition will be shown in detail. The transformation kinetic has been monitored by in situ sheet resistance measurements that, coupled to structural characterisation, allowed to evidence the presence of an intermediate phase before the C54 formation. The temperature of the C54 phase formation decreases with a Ta concentration of 4.5·1015 cm−2 and μ-Raman images of partially transformed samples indicates that the density of C54 grains in presence of Ta is about one order of magnitude higher with respect to pure Ti/Si samples.

The processes of nucleation and growth of the C54 TiSi2 phase into the C49 phase in thin films have been studied by electrical measurements and micro-Raman spectroscopy. The Raman spectra have been acquired scanning large silicide areas (100×50 μm2) in step of 0.5 μm. Images showing the evolution of the C54 grains during the transition have been obtained for temperatures between 680 and 720 °C and the transformed fraction, the density and the size distribution of the C54 grains have been measured as a function of the temperature and the annealing time. The activation energies for the nucleation rate and the growth velocity have been determined obtaining values of 4.9 ± 0.7 eV and 4.5 ± 0.9 eV, respectively.

Molybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (∼2610°C) and low coefficient of thermal expansion (5×10−6/°C, at 20 °C) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.

A new technological method of producing the Ni silicide with metal-like conductivity by deposition of a thin Si film over an ultrathin Ni prelayer at low temperature has been developed. The interaction of a metallic Ni with the Si atoms provided by the deposition source leads to the formation of the Ni-rich silicide phases immediately after the onset of Si deposition. Continued Si deposition results in the transformation of the Ni-rich silicide phases into the more Si-rich ones which implies that the phase composition is controlled by the Ni-to-Si concentration ratio rather than temperature. After Ni is completely consumed, the Si grains grow epitaxially on the disilicide crystals. The silicide layer has been studied in detail with respect to both the dynamics of the silicide growth and the electrical properties. The Ni silicide resistivity was found to be 2×10-4Ωcm. The technique has advantages in two respects: it provides a high crystallinity Si film and allows fabrication of an ohmic contact directly on the substrate thus leaving the front surface of the film available for the formation of the active device junction.

The internal structures of various (ZrO2)x(SiO2)1-x alloys (x ≤ 0.5) were investigated. A remote plasma enhanced-metal organic chemical vapor deposition (RPEMOCVD) process was used to deposit films with varying alloy composition on Si(100) substrates. This study indicates that for the glassy silicate phase, g-ZrSiO4, a glass transition temperature, Tg, exists between 800°C and 900°C at which phase separation into the end-member components, SiO2 and ZrO2, occurs.

ZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.

It is generally known that nucleation effects strongly influence the CoSi to CoSi2 phase transition. According to classical nucleation theory, the small difference in Gibbs free energy between the CoSi and CoSi2 phase is responsible for the nucleation barrier. Adding elements that are soluble in CoSi and insoluble in CoSi2 will influence the entropy of mixing, and thus change ΔG. In this way, the height of the nucleation barrier may be controlled.

By depositing Fe or Ge (respectively replacing Co and Si in the CoSi lattice) in between the Co and the Si substrate, we were able to increase the nucleation barrier. In the presence of Ni, the nucleation barrier is lowered, and low-resistive disilicide is formed at lower temperatures.

The electrical and reliability characteristics of ultra-thin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si-D bond at the Si/SiO2 interface. This nitridation process of gate dielectric using ND3 has considerable potential for future ultra large scaled integration (ULSI) device applications.

Using high resolution TEM (HRTEM), we identified some process induced ‘weak spots’ in SiO2 layers: First, we observed thinning in the periphery of the transistor, i. e. near the boundary to the shallow trench isolation. At the boundary to the shallow trench, the Si substrate gradually changes its orientation from <100> to <110>, which results in an unexpected oxidation behavior in this region. Secondly, we observed the intrusion of poly-Si grains from the gate into the gate oxide, resulting in local thinning of the dielectric. Using image simulations, we show that conventional high resolution TEM can reveal the interface roughness only to a very limited extend.

We have studied the effects of nitridation on the leakage current of thin (7-8 nm) gate or tunnel oxides. A polarity dependence of the tunneling current has been found this behavior is related to the presence of a thin silicon oxynitride layer at the SiO2/Si-substrate interface. The oxynitride layer lowers the tunneling current when electrons are injected from the interface where the oxynitride is located (substrate injection). The current flowing across the oxide when electrons are injected from the opposite interface (gate injection) is not influenced by the oxynitride. The increase of nitrogen concentration leads to a decrease of the tunneling current for substrate electron injection.

If chemically vapor deposited high permittivity materials such as TiO2 and Ta2O5 are to gain wide acceptance as alternatives to SiO2 gates in silicon MOSFETs, the interface between the deposited high-k material and the silicon must be abrupt and have a low density of electrically active defects. Unfortunately, the process for depositing these materials often produces an unacceptably thick, low-permittivity amorphous layer at the interface, which reduces the effectiveness of the high-k material and often contains unacceptably large numbers of charge states. One way to prevent this layer from forming is to deliberately introduce a very thin layer of Si3N4 to act as a diffusion barrier prior to deposition of the high-k material. Previous work has shown nitrides to have high concentrations of traps and interface states, but these films also had considerable oxygen contamination, particularly at the nitride-silicon interface. In this paper, we show that direct thermal nitridation of the silicon surface in ammonia can provide a low interface state density surface that is also an excellent diffusion barrier. A key feature of this process is the various techniques needed to obtain very low oxygen incorporation in the Si3N4. Even at the Si3N4-Si interface, the oxygen content was near the detection limits (0.5%) of Auger Electron Spectroscopy (AES). The nitride films were grown in a range of temperatures that resulted in self-limited thicknesses from a few monolayers to a few nanometers. These films were then characterized by Auger, Time-of-Flight SIMS, and in the case of the thicker films, capacitance-voltage techniques on both n- and p-type silicon substrates. The data shows very low levels of oxygen contamination in the nitride films and low interface state densities in capacitors fabricated from this material.

This paper reports a procedure for low-temperature nitridation of silicon dioxide (SiO2) surfaces using species produced by catalytic decomposition of NH3 on heated tungsten in catalytic chemical vapor deposition (Cat-CVD) system. The surface of SiO2/Si(100) was nitrided at temperatures as low as 200°C. X-ray photoelectron spectroscopy measurements revealed that incorporated N atoms are bound to Si atoms and O atoms and located top-surface of SiO2.

The enhanced formation of the C54-TiSi2 phase by the addition of small amounts of refractory metal (Tm = Mo, Ta, Nb,..) has often been ascribed to a template mechanism from the C40 TixRm1−xSi2 or the (Ti,Rm)5Si3 phase. Due to lattice matching conditions, the presence of either of these phases is thought to lower the interface energies with certain orientations of the C54-TiSi2 grain and, thereby, possibly lower the nucleation barrier of the C54-TiSi2 phase. These proposed template mechanisms are specifically tested in the present work through a study of the nucleation of TiSi2 phase(s) in contact with a pre-existing C40 Ti0.4Mo0.6Si2 or Ti5Si3 layer. No identifiable enhancement in the C54-TiSi2 nucleation was observed which could be attributed to templates. Instead, the nucleation temperature of the C54-TiSi2 phase appeared to be correlated with the grain size of the C49-TiSi2 layer, independent of whether Rm was present. These results are suggestive that the primary mechanism for the enhanced formation of the C54 phase by refractory metals is a reduction in the grain size of the C49 TiSi2phase, likely due to altered kinetics.

Nickel disilicide layers were prepared by nickel ion implantation into silicon substrates using a metal vapor vacuum arc ion source at various beam current densities to an ion dose of 6×1017 cm−2. Characterization of the as-implanted and annealed samples was performed using Rutherford backscattering spectrometry, x-ray diffraction, electrical resistivity and Hall effect measurements. The temperature dependence of the sheet resistivity and the Hall mobility from 30 to 400 K showed peculiar peak and valley features varying from sample to sample. A two-band model was proposed to explain the observed electrical transport properties.

A new system that incorporates many benefits of large batch furnaces (high quality films, growth of wet and dry oxides, chlorine capability, and low cost) into a single wafer processing module has been developed at SVG Thermal Systems. The problems associated with wafer temperature measurement and control in traditional lamp based RTP systems are avoided by utilizing a hot wall isothermal processing chamber. Unique fixturing is used to minimize thermal stress on the wafer during ramping. High quality gate oxides ranging in thickness from 20Å to 40Å have been grown in this system using both wet and dry oxidation ambients, with and without chlorine. Thin oxides grown in dry oxygen had 1-sigma uniformities in the range of 0.72-0.95%, while oxides grown in oxygen/HCl (1-3%) had uniformities of 0.80%. Steam grown oxides demonstrated growth rates of 100Å/min at 900°C and uniformities of 0.62%. Dry oxides annealed in NO and N2O had peak nitrogen incorporation levels ranging from 0.5 to 5.1 atomic percent depending on anneal ambient, temperature and time.

Material interaction during integration of tungsten gate stack for 1 Gb DRAM was investigated by Transition Electron Microscopy (TEM), X-ray Diffraction analysis (XRD) and Auger Electron Spectroscopy (AES). During selective side-wall oxidation tungsten gate conductor undergoes a structural transformation. The transformation results in the reduction of tungsten crystal lattice spacing, re-crystallization of tungsten and/or growth of grains. During a highly selective oxidation process, a relatively small but noticeable amount of oxygen was incorporated into the tungsten layer. The incorporation of oxygen is attributed to the formation of a stable WO x (x<2) composite.

This article reports on the physical and electrical properties of yttrium silicate, which is a possible high-k replacement for the SiO2 gate dielectric in CMOS devices. The yttrium silicate (Y-O-Si) films are formed by sputtering yttrium onto clean silicon, annealing in vacuum to form yttrium silicide and then oxidizing in N2O to form the silicate. Shifts in the Y 3d, Si 2p and O 1s photoelectron spectra with respect to Y2O3 and SiO2 indicate that the films are fully oxidized yttrium silicate. FTIR results that reveal a Si-O stretching mode at 950 cm−1 and Y-O stretching modes in the far-IR are consistent with XPS. XPS and FTIR results are in accordance with the donation of electron density from the yttrium to the Si-O bond in the silicate. The yttrium silicate films contain a fixed charge density of ∼9×1010 cm−2 negative charges as calculated from measured C-V behavior. The properties of ultra-thin yttrium silicate films with an equivalent silicon dioxide thickness (electrical) of ∼1.0 nm will be discussed elsewhere.