Motivation

Modern transceivers for wireless communication consist of many building blocks, including low-noise amplifiers, mixers, frequency synthesizers, filters, variable-gain amplifiers, power amplifiers, and even digital signal processing (DSP) chips. Each of these building blocks has a different specification, imposes different constraints, and requires different design considerations and optimization. As a result, wireless transceivers have been exclusively implemented using hybrid technologies, mainly GaAs for low noise and high speed, bipolar for high power, passive devices for high selectivity and CMOS for DSP at the baseband. While taking advantage of the best in each technology, this hybrid combination unfortunately requires multi-chip modules and off-chip components, which not only are costly and bulky, but also consume a lot of power.

However, recent development and advance scaling of deep-submicron CMOS technologies have made it more feasible and more promising to implement a single-chip CMOS wireless transceiver. This single-chip integration is particularly attractive for its potential in achieving the highest possible level of integration and the best performance in terms of cost, size, weight, and power consumption.

Among the many design issues and considerations in single-chip CMOS integration is the aggressive scaling of the channel length. According to the Semiconductor Industry Association's roadmap in November 2001, the channel length will be scaled to be as small as 65 nm in 2007, as illustrated in Fig. 1.1.