Introduction

Performing transistor-level transient simulation of frequency synthesizers normally takes a very long time. As a result, it is typically neither practical nor worthwhile to verify the transient performance of the synthesizers with simulations at the transistor level. Alternatively, carrying out system-level simulations or behavioral simulations can be quite important and critical in optimizing design parameters and in boosting up the efficiency and verification of a design. A suggested design procedure for PLLs is shown in Fig. 5.1. The first step is the specification definition, in which all the critical parameters are determined, including architecture, output frequency, input frequency, division ratio N, VCO gain KVCO, charge pump current ICP, and loop bandwidth BW. After defining the specification, mathematical models and behavioral models can be constructed for each building block, and for the whole synthesizer, to verify the stability. The issues and considerations of system simulations of RF frequency synthesizers are discussed in this chapter.

Linear model

The block diagram of a third-order synthesizer is shown in Fig. 5.2. The critical parameters to be defined first are the division ratios N1 and N2 as the synthesizer system. The division ratios are determined based on the relation between the input reference and the output frequencies. If a desired output clock frequency is to be 3.2 GHz, while the input clock frequency is 100 MHz, this leads to the division ratios N1 and N2 to be 1 and 32, respectively.