Pipelining VeSPA

An overview of the structure of a pipelined processor was provided in the previous chapter. We will now fill in the details and add flesh to the skeletal concepts introduced earlier, at the end of which we will have developed a block-level structure for the processor that can be implemented in Verilog. Our processor will consist of the following five pipelined stages, the instruction fetch (IF) stage, the instruction decode (ID) stage, the execute (EX) stage, the memory (MEM) stage, and the write back (WB) stage. We will interchangeably refer to these as the first through the fifth stages, respectively.

Such an instruction pipeline may be defined at the behavioral level or the structural level. At the behavioral level, the hardware may be modeled as a finite state machine that performs IF in the first stage, ID in the second, and so on, with Moore outputs generated in each stage, corresponding to the control signals that are used to activate the instructions. An example of such a description is provided for a simple processor in a book on VHDL-based design by Roth (see the Further reading section at the end of this chapter).

Instead of such an approach, we choose to describe the circuit at the structural level in this chapter, in order to get the reader ‘closer to the hardware’. This structural description shows interconnections between blocks such as ALUs, MUXs and registers, as well as more fundamental gates.