Introduction

The phase comparison path in a phase-locked loop detects the phase delay between the reference and the feedback oscillation. Since the time delay between the edge of the reference signal and the subsequent edge of the divider signal is measured, the phase delay is a signal sampled at the reference frequency.

The phase comparison can be performed either in the analogue or in the digital domain. The analogue implementations, although they use logic circuits such as the XOR gate or the tri-state PFD, provide an analogue value of the phase error. Instead, digital implementations derive the phase error by subtracting the instantaneous count of the reference counter from that of the feedback counter. After the phase error is detected, it is filtered and applied to the VCO tuning port.

The type of phase detection affects the in-band noise, the level of spurious tones and the lock acquisition behaviour. The non-linearity of the phase comparison path may seriously degrade both noise and spurs. Thus, it has to be accurately examined and attenuated.

Phase comparison path

An analogue phase detector is, typically, a logic circuit, which generates pulses of duration equal to the time difference between the REF and the DIV edges. The phase comparison path is sketched in Figure 9.1(a). The phase detector output is low-pass filtered, to extract its average value, or it is accumulated into an integrator in a type-II loop.