The historical CMOS scaling scenario

Complementary Metal Oxide Semiconductor (CMOS) technology is nowadays the backbone of the semiconductor industry worldwide and the enabler of the impressive number of electronic applications that continue to revolutionize our daily life. The pace of growth of CMOS technology in the last 40 years is clearly shown in the so-called Moore's plot (see Fig.1.1 [1]), reporting the historical trend in the number of transistors per chip, as well as in the trends of many other circuit performance metrics and economic indicators.

Key to the success of CMOS technology is the extraordinary scalability of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The word scaling denotes the possibility, illustrated in Fig.1.2 and Table1.1, of fabricating functional devices with equally good or even improved performance metrics but smaller physical dimensions. The design of scaled transistors starting from an existing technology has been driven initially by simple similarity laws aimed to maintain essentially unaltered either the maximum internal electric field (hence, to a first approximation, the device reliability) or the supply voltage (hence the system integration capability) [2].

According to these two scaling strategies, defined in Table1.1, all the lateral (primarily the gate width, W, and length, LG) and the vertical physical dimensions (the thickness of the gate dielectric, tox, and the junction depth, xj) should decrease from one technology generation to the next by a factor α, thus yielding an increase of the number of transistors per unit chip area by a factor of α2.