This issue of the MRS Bulletin focuses on current interconnect metallurgies practiced in the manufacturing of integrated circuits (ICs). The issue should serve as a reference for researchers, scientists, engineers, and those who are not familiar with the IC arena.

Al-metallization requires special attention due to its wide usage in logic and memory circuits. Logic requirements drive technology toward improved circuit performance while memory improvements require high device and wiring densities. As the dynamic random access memory (DRAM) evolves from 64 Mbits to 256 Mbits, ultralarge-scale integrated (ULSI) wiring will decrease to below sub-0.3 μm in dimensions. Such circuits require robust, reliable back end of the line (BEOL) technology that meets high-performance, low-cost, stringent electromigration requirements. We feel that several of these emerging interconnect fabrication techniques have reached a sufficient level of maturity to warrant a reasonable exposition. We will concentrate on metallization systems in this issue, leaving a discussion of dielectrics for the future, due to space limitations.

The semiconductor industry has relied on aluminum technology since the 1960s because it is a well-established, low-cost technology. Early improvements in the electromigration resistance of Al lines by the addition of Cu impurities after 1971 helped this metallurgy to endure further feature size reductions, without degradation of reliability. However, the relentless reduction in via and line size once again may bring into question the limitation of Al reliability. As a result, work on alternate low-resistivity and high-electromigration-resistant metals like Cu is continuing in parallel.

Titanium nitride (TiN) has been recognized as an excellent barrier material in various metallization structures of advanced microelectronic devices. TiN serves as a nucleation/glue layer as well as a barrier against WF6 attack in W plug filling. It serves as a diffusion barrier during or after high-temperature Al reflow processing for contact and via filling. TiN is considered as a diffusion-barrier material for Cu metallization as well. In addition, it is utilized as an antireflection coating layer, especially on top of Al, an application that will not be discussed in this article.

TiN films must conform to the extreme topographies used in devices in order to guarantee void-free plug formation as well as Jow junction leakage. This should be achieved with the thinnest films possible in order to reduce interconnect stack thickness and to lower contact or via resistance. (The TiN resistivity is higher than that of the other components of the metallization—Ti, Al, or W.) In addition, the good barrier properties must be retained following various thermal cycles used in multilevel metallization. Finally, the metallization must be manufacturing-worthy, namely, it should be reliable and reproducible, it should have a very low particle content, and it should have a low cost of ownership.

At present, TiN is mainly deposited by physical vapor deposition (PVD) via reactive sputtering. However, the poor conformality of sputtered TiN films over extreme topography limits the use of this deposition technique for deep sub-0.5 μm applications, especially those with features that have high aspect ratios.

Collimated sputtering is a physical vapor deposition (PVD) method where a collimator is inserted between a conventional “full-face-erosion” sputtering target and a substrate (Figure 1). The collimator is a plate of hexagonal cells that acts as a filter to remove obliquely incident atoms before they arrive at the substrate. Only material with a nearly normal incidence trajectory may pass through the collimator and deposit on the substrate. Collimated sputtering was initially evaluated for conductor-level depositions in order to improve the filling of recessed features. Although the method has been successfully used to fill damascene structures, depositing thick conductor films is inefficient because most of the sputtered material is captured by the collimator, causing the collimator to clog quickly, necessitating frequent replacement.

A more common use of collimated sputtering is associated with the deposition of thin “liner” films. For example, thin, collimated aluminum alloy films have been used as underlayers for aluminum reflow processes. Also, collimated Ti/TiN films are used as contact/adhesion layers for chemically vapor-deposited (CVD) W metallization. Collimation provides better bottom and sidewall coverage for small, high aspect-ratio features than conventionally sputtered films do.

Coliimated sputtered films often exhibit unique properties because the angle of incidence of depositing atoms is controlled. Collimated AlMg alloys have superior electromigration resistance compared to noncollimated AlMg films. Collimated TiN films appear to exhibit denser grain structures when compared to films deposited with higher amounts of obliquely incident flux (Figure 2).

As the feature size of ULSI (ultralarge-scale integration) circuit devices shrinks, interconnects need to be scaled to maximize the wiring density and wire ability. This increased density leads to smaller contacts or via holes connecting the wires. The reduction in size increases the aspect ratio of these features for the same dielectric thickness. Conventional physical vapor deposition (PVD) techniques such as sputtering are unable to fill high aspect-ratio contacts/vias with aluminum conformally, as shown in Figure 1. This poor conformity is attributed to the shadowing effect by already-deposited nondirectional sputtering atoms and leads to void formation and open failures. Chemical vapor deposition (CVD) is a solution for achieving conformal filling.

This is a prime reason why CVD has been investigated since the 1980s and why a large number of metals have been proposed. Above all, because tungsten as a refractory metal has high resistance to electromigration (EM) failures and tungsten hexafluoride (WF6) as a source gas has some advantages in manufacturing, for example, high vapor pressure (boiling point = 17.4°C) and purity, W-CVD with WF6 based on H2 or SiH4 reduction has been widely studied. Blanket W-CVD has been used for actual via-hole filling for 0.5-μm devices. Figure 2 shows a cross-sectional view of five-level interconnects using W plugs in 0.35-μm devices. Another advantage of W-CVD is that W deposits selectively into via holes if a low flow-rate ratio of reductants to WF6 is used.

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.

Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.

This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.

In an integrated circuit (IC), the global interconnects are used to run power and ground to the individual transistors as well as to send signals across the chip. The width of interconnects can vary, depending on the current that is carried by the interconnect. Figure 1 shows a cross section of a double-metal complementary metal oxide semiconductor (CMOS) circuit illustrating the major components of a multilevel metallization circuit. The global interconnect connects to the diffusion and polysilicon gates through the contacts. The intermetal dielectric electrically separates the different levels of interconnect. The connection between the global interconnects at adjacent levels is made through the vias. The choice of a global interconnect for a multilevel metallization forces one to consider how the interaction between the various components of this system can affect the performance of the interconnect. For example, the intermetal dielectric changes the mechanical stress in the interconnect; the presence of W plugs in vias can affect the electromigration resistance of interconnects. In this article, we will examine the problems that are encountered when using Al alloys as a global interconnect and illustrate how the material properties can be modified to solve these problems.

As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely in deference to the costs associated with converting existing semiconductor lines to copper-compatible facilities. In addition to tooling costs, there is a learning curve for copper systems that remains to be established for device reliability, field failures, yield learning, and process maturation. On the other hand, existing fabs are already compatible with aluminum metallurgies, and there is a rich history of reliability and yield data.

This change in direction creates two immediate needs: (1) the need to fill small-diameter vertical interconnects (vias) with void-free aluminum and (2) the need to remove the top surface aluminum resulting from its blanket deposition (overburden) following the metal fill. In addition, for high circuit-density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill.

A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).

The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.

In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.

Problems with mechanical stress in very large-scale integration (VLSI) interconnections appeared quite early in the history of the industry. Failures were observed in the dielectric itself, in the die, and in metal lines. Various process and design changes were made to fix the problems, but the continuing shrinking of dimensions and increased complexity of interconnection structures have resulted in recurrence of old problems, the appearance of new ones, and increasing difficulty in developing fixes. The choices for interconnection materials and processes have become increasingly constrained. The shift from hermetic to plastic packaging reduces the choices for passivation materials. The reduced dimensions for the active devices and the corresponding shortening of diffusion distances limit the “thermal budget”; interconnection processing must be carried out quickly and at relatively low temperatures. The reduced space available for interconnections has resulted in the use of high aspect ratios, multiple layers of metal, and the need for planarization. These all lead to further constraints on materials and processes. An additional complicating factor is the continuing effort to reduce the time from initial design to marketing the product. Since many mechanical-stress-induced problems are wear-out reliability problems, they may require extensive testing for detection. If a problem is not found until late in the product cycle, the economic consequences may be severe. To avoid costly late detection of problems and frantic scrambles for fixes, it is essential to have a clear understanding of the various origins of mechanical stress, the behavior of various materials and interfaces under stress, and the potential failure mechanisms.

Open interconnections on integrated circuits (ICs) are a serious and ubiquitous problem throughout the micro-electronics industry. The efforts to understand the mechanisms responsible for producing open interconnections and to develop analytical methods to localize them demonstrate the concern manufacturers have for this problem. Multiple layers of metallization not only increase the probability that an open conductor or via will occur because of the increased number of interconnections and vias but also increase the difficulty in localizing the site of the failure because upper layers may mask the failure site.

Rapid failure analysis of open-conductor defects is critical in new product development and reliability assessment of ICs where manufacturing and product development delays can cost millions of dollars a day. In this article, we briefly review some standard failure analysis approaches and then concentrate on new techniques to rapidly locate open-conductor defects that would have been difficult or impossible to identify using earlier methods. Each method is described in terms of the physics of signal generation, application, and advantages and disadvantages when compared to existing methods.

Interconnects technology and back-end processing moved to the center stage of very large-scale integration (VLSI) technology in the mid-1980s. At that time, the critical dimensions dropped below 1 μm while the chip size and complexity increased to a level where interconnects were recognized to be a limiting factor. As dimensions decreased, the step coverage of sputtered aluminum inside contacts and via-contact holes decreased and alternative technologies were studied. The increasing cost of ownership (COO) of single-wafer Al sputtering processes also supported the search for alternative technologies, such as tungsten chemical vapor deposition (CVD) for via contacts and plugs (Figure 1). Only recently have all the W CVD process steps been optimized to lower cost without loss of reliability and/or performance. The development of cluster tool technology and multiwafer process modules also allowed reliable and cost-effective utilization of the W/Al technology.

Tungsten technology for VLSI circuits became complementary to that of aluminum. Tungsten thin-film resistivity ρw = 7–8 μΩ cm is much higher than that of aluminum ρAl = 3–4 μΩ cm, introducing large W interconnect resistance-capacitance (RC) delays compared to Al. Therefore, tungsten is not favorable for high-speed global-interconnect schemes. However, tungsten is suitable for local interconnects where the impedance of the driving transistors is dominant and the RC interconnect delay is less significant. Tungsten is also suitable for contact filling, in which the via resistance is negligible. For these applications, tungsten became a dominant technology and was integrated with the aluminumalloy-based technology used for global interconnects.