In this work we present a physically based quantum correction model for highly scaled double gate (DG) CMOS devices. In contrast to previous work, our quantum correction model is based on the bound states that form in the Si film. The Eigenenergies and expansion coefficients of the wave functions are tabulated for arbitrary parabolic approximations of the potential in the structure. This enables a highly efficient use for TCAD applications.

Silicon on insulator (SOI) substrate is a key materials for nano-scaling IC device and the requirement for its crystal structure and quality is really high. Nanothick silicon thin film can be transferred onto a handle wafer from a donation wafer to form a SOI wafer after this process including hydrogen implantation of donation wafer, wafer bonding, and thermal treatment at moderately high temperatures of 400 to 600 degree centigrade. The expansion of the hydrogen molecular evolving from the implanted hydrogen ions interacting with silicon dangling bonds and trapped inside the microcavities located near the ion projected range resulted in exfoliation of the silicon thin film in the final heating step. The hydrogen molecules inside the microcavities tend to expand along the bonded interface rather than radially to form individual blisters. Finally, the fracture failure of ion implanted area parallel to the bonded interface near the projected ion range is formed by the sideway expansion of the cavities due to the diffusion supply of implanted hydrogen excited by thermal energy. Microwave processing can lower the activity energy to speed the chemical reaction so that it leads the format of microcavities occurring at low temperature by directly exciting the implanted hydrogen ions by microwave energy and also results in decreasing the critical dosage for layer splitting. However, microwave irradiation alone at room temperature causes the formation of lots of nucleus sites of micro-voids filled by hydrogen molecule which is immobility in silicon resulting in the issue of uniformity of transferred layer. In this study, the hydrogen implanted silicon substrate was irradiated by microwave at low temperature (200 degree centigrade) rather than microwave alone to co-activate the implanted hydrogen ions in silicon to increase not only kinetic energy but also mobility to successfully achieve a completely transferred layer in a short time.

We report the use of nickel-platinum silicide (NiPtSi) as a source/drain (S/D) material for strain engineering in P-MOSFETs to improve drive current performance. The material and electrical characteristics of NiPtSi with various Pt concentrations was investigated and compared with those of NiSi. Ni0.95Pt0.05Si was selected for device integration. A 0.18 μm gate length P-MOSFET achieved a 22% gain in IDsat when Ni0.95Pt0.05Si S/D is employed instead of NiSi S/D. The enhancement is attributed to strain modification effects related to the nickel-platinum silicidation process.

As conventional materials in CMOS manufacturing, Si as a gate material and SiO2 as a gate dielectric, approach their performance limit, the search for new materials becomes key point. Patterning of the new stacks containing these materials require both new plasma etch chemistries and new approaches.

We propose a BCl3/N2 based plasma mixture for the advanced gate patterning (in this case pure Ge gates and TaN metal gates). There are three reasons to select this combination:

a) The gas mixture generates Cl* species able to etch a diversity of materials, b) it is selective towards Si due to formation of passivating Si-B bonds and c) it improves profile control possibly by formation of a passivating BN-like film on feature side walls. It was found that BCl3 in presence of N2 results in a film deposition if no bias is applied to the substrate (i.e. there is no ion bombardment). The film is hexagonal BN-like since the characteristic peaks corresponding to the in-plane B-N and out-of-plane B-N-B bonds were found in FTIR spectra. The composition of the film surface as found by XPS is B, N and O (as no O2 is present in the plasma it may be a result of oxidation in the atmosphere), the amount of Cl is approx. 1%. The film is soluble in water that makes its removal easy. The deposition rate can be as high as 300 nm/min depending on plasma power, pressure, flow rates and BCl3 to N2 ratio.

We propose to use the BCl3/N2 mixture to etch materials too sensitive to Cl-based plasma. Pure BCl3 plasma might distort gate profiles, as materials are etched in a lateral direction as well, this is the case, e.g. for pure Ge gates. Addition of small amount of nitrogen (5% to 10%) to the BCl3 plasma preserves the vertical profile, apparently by the formation of a passivating BN-like layer on the vertical surfaces where there is no ion bombardment. Too high nitrogen concentration results in positively sloped gate profile or even in the etch stop that could be attributed to the too high deposition rate that exceeds the etch rate. All experiments have been performed in Lam Versys 2300 etch chamber.

We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 °C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.

Detailed investigations of strain generation and relaxation in Si films grown on thin Si0.78Ge0.22 virtual substrates using Raman spectroscopy are presented. Good virtual substrate relaxation (>90%) is achieved by incorporating C during the initial growth stage. The robustness of the strained layers to relaxation is studied following high temperature rapid thermal annealing typical of CMOS processing (800-1050 °C). The impact of strained layer thickness on thermal stability is also investigated. Strain in layers below the critical thickness did not relax following any thermal treatments. However for layers above the critical thickness the annealing temperature at which the onset of strain relaxation occurred appeared to decrease with increasing layer thickness. Strain in Si layers grown on thin and thick virtual substrates having identical Ge composition and epilayer thickness has been compared. Relaxation through the introduction of defects has been assessed through preferential defect etching in order to verify the trends observed. Raman signals have been analysed by calibrated deconvolution and curve-fitting of the spectra peaks. Raman spectroscopy has also been used to study epitaxial layer thickness and the impact of Ge out-diffusion during processing. Improved device performance and reduced self-heating effects are demonstrated in thin virtual substrate devices when fabricated using strained layers below the critical thickness. The results suggest that thin virtual substrates offer great promise for enhancing the performance of a wide range of strained Si devices.

In this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.

We report thin SGOI (Silicon Germanium on Insulator) with 65% Ge concentration p- MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using Ni-germanosilicide Schottky S/D (source/drain) and HfO2/TaN gate stack integrated with conventional self-aligned top gate process. Unlike high temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic, low gate leakage current and hence, well-behaved transistor performance. In addition, SOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current of the MOSFET.

According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

Silicon wafers with shallow trench isolation structures 3700Å deep were self-implanted with silicon at 40keV, and a dose of 1E15/cm2. This produced an amorphous layer 1000Å deep. The samples were subsequently annealed at temperatures ranging from 750°C to 900°C. The excess interstitials can recombine at the “surface” created by the proximity to the trench sidewall. Plan-view TEM was used to quantify the dislocation distribution as a function of distance from the trench sidewall. It was found that there was no measurable change in defect density as a function of distance from the trench. This was true for both the 20 minute isochronal anneal, and the isothermal study 750°C. This suggests there is a relatively weak recombination of interstitials at the surface. This is surprising given most of the TCAD models assume a very fast surface recombination velocity.

A novel field effect transistor (FET) that uses 3-dimensional (3-D) embedded gate fingers – the Screen-Grid Field Effect Transistor (SGFET) – is proposed. The gating action of the SGFET is based on the design of multiple gating cylinders into the channel region, perpendicular to the current flow. Such configuration allows a full 3-D gate control of the current which improves the device characteristics by increasing the gate to channel coupling. Initial investigations of the SGFET using 3-D TCAD TaurusTM simulation software are presented in this paper. The results indicate that the proposed SGFET offers the possibility of downscaling without degrading the output characteristics. A comparison between the SGFET and both bulk and SOI MOSFETs shows the superior characteristics of the SGFET for low power operation.

Using an extensive series of first principles calculations, we have developed general models for the change in energy of boron migration state via interstitial mechanism as a function of local alloy configuration. The model is based on consideration of both global strain compensation as well as local effects due to nearby arrangement of Ge atoms. We have performed KLMC (Kinetic Lattice Monte Carlo) simulations based on change in migration energy to explain the reduced B diffusion in strained SiGe and compared our results to experimental observations. These models include significant effects due to both global stress and local chemical effects, and accurately predict the B diffusivity measured experimentally in strained SiGe on Si as a function of Ge content.

Convergent electron beam diffraction (CBED) has been successfully applied to measure strain/stress in the channel area in PMOS semiconductor device with embedded SiGe (eSiGe) for 65nm technology. Reliable results of strain/stress measurements in the channel area have been achieved by good fitting of experimental CBED patterns with theoretical calculations. Stress measurements from CBED are in good agreement with simulations. A compressive stress as high as 823.9 MPa was measured in the <110> direction in the channel area of a PMOS device with eSiGe with 15% Ge and a thickness of 80nm. Stress measurements from CBED also confirm that the depth of the eSiGe and defects such as dislocation loops within the eSiGe relax strain/stress within the film and reduce strain/stress in the channel area.

The rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective approach to enable significant performance improvements at similar off-state leakage. In this paper we describe how strain effects are modeled within the context of TCAD process and device simulation. We also use TCAD simulations to review some of the common approaches to engineer strain in MOSFETs and to explain how strain impacts device and circuit characteristics.

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: <110> and <100>. This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.

The temperature rise in SOI has been measured on two successive generations. This work shows that self-heating effects become less and less severe with both MOSFET and power supply voltage scaling.

Hybrid orientation substrates make it possible to have a CMOS technology in which nFETs are on (100) Si (the Si orientation in which electron mobility is the highest) and pFETs are on (110)-oriented Si (the Si orientation in which hole mobility is the highest). This talk will describe a new amorphization/templated recrystallization (ATR) method for fabricating bulk hybrid orientation substrates. In a preferred version of this method, a silicon layer with a (110) orientation is directly bonded to a Si base substrate with a (100) orientation. Si regions selected for an orientation change are amorphized by ion implantation and then recrystallized to the (100) orientation of the base substrate. After an overview of the ATR technique and its various implementations, we will describe some of the scientifically interesting materials and integration challenges encountered while reducing it to practice.

Sub-100nm gate length silicon and GaN based SOI n-type MOSFET are modeled and simulated using ISE-TCAD (now synopsys_sentaurus). Several silicon SOI structures such as planar fully depleted SOI, FinFET, Tri-Gate MOSFET, cylindrical channel (OMFET) and triangular channel MOSFETs have been studied to compare the structure dependence of the device performance. Silicon and GaN as channel materials are also compared for these different SOI structures for projecting the device performance for very short channel SOI MOSFETs. Our study shows that for sub-100nm gate length, GaN based transistors have better Ion/Ioff ratio and higher small signal transconductance than silicon based transistors. And GaN and Si based devices have comparable performance such as sub-threshold slope and threshold roll off, etc. However for sub 20nm gate length, simulation shows that while it is not satisfying for silicon based device for digital applications, GaN based transistors with lower off state leakage current, less short channel effect than Silicon based transistors are still good candidates for digital applications . The TCAD study shows that GaN could be a promising candidate for making very short channel device as the GaN processing technology is advancing.

The impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.

The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.

PFET devices fabricated using embedded SiGe source/drain on (110) silicon substrates have shown significant performance improvement compared to PFETs with embedded SiGe on (100) SOI substrates. In this paper, we report a systematic material characterization on the epitaxial SiGe films, both on blanket and patterned substrates, and corresponding PFET performance data. The SiGe films were deposited in an RTCVD system. The epitaxial growth rate on (110) substrates was 30% lower than on (100), and 30% higher on patterned device wafers compared to blanket wafers. Films were characterized using an array of methods such as High Resolution XRD (for Ge composition, strain and thickness), Auger (for Ge composition), UV Raman microprobe (for strain), AFM (for surface morphology), and TEM (for epi quality). The Ge compositions determined by XRD and Auger are in excellent agreement (15~16%). The amount of strain extracted from the Raman measurements is also consistent with the amount determined by XRD, which is 0.60%, corresponding to a fully strained Si0.85Ge0.15 film. AFM showed much higher RMS and Rmax for the SiGe films on (110) substrates compared to those on (100) substrates. XTEM showed high crystalline quality with very low defect count in the SiGe source/drain and Si channel regions. PFETs with an embedded Si0.85Ge0.15 source/drain on hybrid orientation (HOT) substrates provided a 30% advantage in drive current and a 23% enhancement in ring oscillator speed compared to control devices on (100) SOI wafer.