The motivation for high-k dielectrics

For each new generation in MOS-technology, a recurrent problem has been the so-called “short channel effect.” It occurs when decreasing the gate length such that the edge of the depletion region at drain approaches the source contact close enough for increasing the leakage between source and drain and for decreasing the transistor threshold voltage (Fig. 11.1(a)). For bulk CMOS technology, the standard method to avoid this issue has been to increase the doping in the channel region in order to decrease the depletion region width of the drain junction. This measure, however, decreases the capacitive coupling between gate and channel and lowers the share of the gate voltage falling across the semiconductor channel. As a consequence, the sub-threshold slope decreases, which in turn slows down the switching speed of the transistor. Furthermore, increased doping levels in the channel give rise to higher scattering probabilities and lowered charge carrier mobility. These problems can be avoided by decreasing the thickness of the gate oxide in order to increase the capacitance between gate and channel such that the oxide capacitance becomes much larger than the channel capacitance and gives a major share of the applied gate voltage to the semiconductor. Measures along these lines were possible until the gate length downscaling reached about 45 nm. At this landmark, the SiO2 dielectric needed to reach a thickness of about 1.5 nm, which gave rise to unacceptable gate leakage levels (Taur et al., 1998; Iwai and Ohmi, 2002; Iwai, 2009; Wong and Iwai, 2006; Frank, 2011).